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From: Peter Maydell <peter.maydell@linaro.org>
To: Sergey Fedorov <serge.fdrv@gmail.com>
Cc: Fabian Aggeler <aggelerf@ethz.ch>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	QEMU Developers <qemu-devel@nongnu.org>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	Greg Bellows <greg.bellows@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources
Date: Mon, 25 Aug 2014 13:25:27 +0100	[thread overview]
Message-ID: <CAFEAcA8_YOrPqc-t8jkQ-1Ezm8a-CR7qAxi3fM_iiBjAmceZVA@mail.gmail.com> (raw)
In-Reply-To: <53FAFEEA.2090009@gmail.com>

On 25 August 2014 10:16, Sergey Fedorov <serge.fdrv@gmail.com> wrote:
> On 22.08.2014 14:29, Fabian Aggeler wrote:
>> Preparing for FIQ lines from GIC to CPUs, which is needed for GIC
>> Security Extensions.
>>
>> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
>> ---
>>  hw/intc/arm_gic.c                | 3 +++
>>  include/hw/intc/arm_gic_common.h | 1 +
>>  2 files changed, 4 insertions(+)
>>
>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
>> index 1532ef9..b27bd0e 100644
>> --- a/hw/intc/arm_gic.c
>> +++ b/hw/intc/arm_gic.c
>> @@ -786,6 +786,9 @@ void gic_init_irqs_and_distributor(GICState *s, int num_irq)
>>      for (i = 0; i < NUM_CPU(s); i++) {
>>          sysbus_init_irq(sbd, &s->parent_irq[i]);
>>      }
>> +    for (i = 0; i < NUM_CPU(s); i++) {
>> +        sysbus_init_irq(sbd, &s->parent_fiq[i]);
>> +    }
>
> Hi Fabian,
>
> I would suggest to provide a way to get a sysbus IRQ/FIQ number for each
> processor, e.g. a dedicated macro. Maybe it could be easier to
> accomplish this by initializing IRQ and FIQ interleaved or by always
> initializing GIC_NCPU IRQs/FIQs.

Using named GPIO registers is the way to go here,
or at least it will be once Peter C's patchset to make
sysbus IRQs just be legacy syntax for GPIOs goes in.

-- PMM

  reply	other threads:[~2014-08-25 12:26 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-22 10:29 [Qemu-devel] [PATCH 00/15] target-arm: Add GICv1/SecExt and GICv2/Grouping Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 01/15] hw/intc/arm_gic: Request FIQ sources Fabian Aggeler
2014-08-25  9:16   ` Sergey Fedorov
2014-08-25 12:25     ` Peter Maydell [this message]
2014-08-22 10:29 ` [Qemu-devel] [PATCH 02/15] hw/arm/vexpress.c: Wire FIQ between CPU <> GIC Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 03/15] hw/intc/arm_gic: Add Security Extensions property Fabian Aggeler
2014-08-25  9:20   ` Sergey Fedorov
2014-08-25  9:39     ` Aggeler  Fabian
2014-08-25 10:07       ` Sergey Fedorov
2014-08-22 10:29 ` [Qemu-devel] [PATCH 04/15] hw/intc/arm_gic: Add ns_access() function Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 05/15] hw/intc/arm_gic: Add Interrupt Group Registers Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 06/15] hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked Fabian Aggeler
2014-08-26 11:47   ` Sergey Fedorov
2014-09-09 23:07     ` Greg Bellows
2014-08-22 10:29 ` [Qemu-devel] [PATCH 07/15] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked Fabian Aggeler
2014-09-09 23:11   ` Greg Bellows
2014-08-22 10:29 ` [Qemu-devel] [PATCH 08/15] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked Fabian Aggeler
2014-09-09 23:10   ` Greg Bellows
2014-08-22 10:29 ` [Qemu-devel] [PATCH 09/15] hw/intc/arm_gic: Implement Non-secure view of RPR Fabian Aggeler
2014-09-09 23:10   ` Greg Bellows
2014-08-22 10:29 ` [Qemu-devel] [PATCH 10/15] hw/intc/arm_gic: Handle grouping for GICC_HPPIR Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 11/15] hw/intc/arm_gic: Change behavior of EOIR writes Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 12/15] hw/intc/arm_gic: Change behavior of IAR writes Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 13/15] hw/intc/arm_gic: Restrict priority view Fabian Aggeler
2014-09-09 23:10   ` Greg Bellows
2014-08-22 10:29 ` [Qemu-devel] [PATCH 14/15] hw/intc/arm_gic: Break out gic_update() function Fabian Aggeler
2014-08-22 10:29 ` [Qemu-devel] [PATCH 15/15] hw/intc/arm_gic: add gic_update() for grouping Fabian Aggeler

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