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From: Peter Maydell <peter.maydell@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org
Subject: Re: [PATCH v5 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max
Date: Fri, 6 May 2022 13:12:01 +0100	[thread overview]
Message-ID: <CAFEAcA998FFitC6=EoP51wg-sirdoAP9MS9Y3OnEfceHcvq0MQ@mail.gmail.com> (raw)
In-Reply-To: <20220505185006.200555-21-richard.henderson@linaro.org>

On Thu, 5 May 2022 at 20:40, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> There is no branch prediction in TCG, therefore there is no
> need to actually include the context number into the predictor.
> Therefore all we need to do is add the state for SCXTNUM_ELx.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum.
> v3: Rely on EL3-no-EL2 squashing during registration.
> v5: Set SCTLR_EL1.TSCXT at user-only startup.
> ---

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM


  reply	other threads:[~2022-05-06 12:14 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 18:49 [PATCH v5 00/24] target/arm: Cleanups, new features, new cpus Richard Henderson
2022-05-05 18:49 ` [PATCH v5 01/24] target/arm: Handle cpreg registration for missing EL Richard Henderson
2022-05-06 11:22   ` Peter Maydell
2022-05-05 18:49 ` [PATCH v5 02/24] target/arm: Drop EL3 no EL2 fallbacks Richard Henderson
2022-05-06 11:36   ` Peter Maydell
2022-05-05 18:49 ` [PATCH v5 03/24] target/arm: Merge zcr reginfo Richard Henderson
2022-05-05 18:49 ` [PATCH v5 04/24] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-05-05 18:49 ` [PATCH v5 05/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-05-05 18:49 ` [PATCH v5 06/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-05-05 18:49 ` [PATCH v5 07/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-05-05 18:49 ` [PATCH v5 08/24] target/arm: Split out aa32_max_features Richard Henderson
2022-05-05 18:49 ` [PATCH v5 09/24] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-05-05 18:49 ` [PATCH v5 10/24] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-05-05 18:49 ` [PATCH v5 11/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-05-05 18:49 ` [PATCH v5 12/24] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-05-05 18:49 ` [PATCH v5 13/24] target/arm: Add minimal RAS registers Richard Henderson
2022-05-05 18:49 ` [PATCH v5 14/24] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-05-05 18:49 ` [PATCH v5 15/24] target/arm: Implement virtual SError exceptions Richard Henderson
2022-05-05 18:49 ` [PATCH v5 16/24] target/arm: Implement ESB instruction Richard Henderson
2022-05-05 18:49 ` [PATCH v5 17/24] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-05-05 18:50 ` [PATCH v5 18/24] target/arm: Enable FEAT_IESB " Richard Henderson
2022-05-05 18:50 ` [PATCH v5 19/24] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-05-05 18:50 ` [PATCH v5 20/24] target/arm: Enable FEAT_CSV2_2 " Richard Henderson
2022-05-06 12:12   ` Peter Maydell [this message]
2022-05-05 18:50 ` [PATCH v5 21/24] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-05-05 18:50 ` [PATCH v5 22/24] target/arm: Enable FEAT_DGH " Richard Henderson
2022-05-05 18:50 ` [PATCH v5 23/24] target/arm: Define cortex-a76 Richard Henderson
2022-05-05 18:50 ` [PATCH v5 24/24] target/arm: Define neoverse-n1 Richard Henderson

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