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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::112c; envelope-from=peter.maydell@linaro.org; helo=mail-yw1-x112c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, 14 Jul 2022 at 15:54, Tobias Roehmel wro= te: > > From: Tobias R=C3=B6hmel > > All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r= 1p3 This should be the last patch in the patchset, so that we only add the new CPU when all the code changes necessary to make it work are present. > Signed-off-by: Tobias R=C3=B6hmel > --- > target/arm/cpu_tcg.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 54 insertions(+) > > diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c > index b751a19c8a..49fb03c09a 100644 > --- a/target/arm/cpu_tcg.c > +++ b/target/arm/cpu_tcg.c > @@ -843,6 +843,59 @@ static void cortex_r5_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexr5_cp_reginfo); > } > > +static const ARMCPRegInfo cortexr52_cp_reginfo[] =3D { > + /* Dummy the TCM region regs for the moment */ > + { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1,= .opc2 =3D 0, > + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, > + { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1,= .opc2 =3D 1, > + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, > + { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .c= rm =3D 5, > + .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, > +}; This is just a copy of the Cortex-R5 impdef register set. The R52 doesn't have the DCACHE_INVAL. Although it does have registers in the ATCM and BTCM encodings, it also has a third CTCM, because it has three TCM regions. You should implement the IMPDEF registers that the CPU actually has, assuming that guest software cares about them. > +static void cortex_r52_initfn(Object *obj) > +{ > + ARMCPU *cpu =3D ARM_CPU(obj); > + > + set_feature(&cpu->env, ARM_FEATURE_V8); > + set_feature(&cpu->env, ARM_FEATURE_V8_R); > + set_feature(&cpu->env, ARM_FEATURE_EL2); > + set_feature(&cpu->env, ARM_FEATURE_PMSA); > + set_feature(&cpu->env, ARM_FEATURE_NEON); > + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); > + cpu->midr =3D 0x411fd133; /* r1p3 */ > + cpu->revidr =3D 0x00000000; > + cpu->reset_fpsid =3D 0x41034023; > + cpu->isar.mvfr0 =3D 0x10110222; > + cpu->isar.mvfr1 =3D 0x12111111; > + cpu->isar.mvfr2 =3D 0x00000043; > + cpu->ctr =3D 0x8144c004; > + cpu->reset_sctlr =3D 0x30c50838; > + cpu->isar.id_pfr0 =3D 0x00000131; > + cpu->isar.id_pfr1 =3D 0x10111001; > + cpu->isar.id_dfr0 =3D 0x03010006; > + cpu->id_afr0 =3D 0x00000000; > + cpu->isar.id_mmfr0 =3D 0x00211040; > + cpu->isar.id_mmfr1 =3D 0x40000000; > + cpu->isar.id_mmfr2 =3D 0x01200000; > + cpu->isar.id_mmfr3 =3D 0xf0102211; > + cpu->isar.id_mmfr4 =3D 0x00000010; > + cpu->isar.id_isar0 =3D 0x02101110; > + cpu->isar.id_isar1 =3D 0x13112111; > + cpu->isar.id_isar2 =3D 0x21232142; > + cpu->isar.id_isar3 =3D 0x01112131; > + cpu->isar.id_isar4 =3D 0x00010142; > + cpu->isar.id_isar5 =3D 0x00010001; > + cpu->isar.dbgdidr =3D 0x77168000; > + cpu->clidr =3D (1 << 27) | (1 << 24) | 0x3; > + cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ > + cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ > + > + cpu->pmsav7_dregion =3D 16; > + > + define_arm_cp_regs(cpu, cortexr52_cp_reginfo); > +} > + > static void cortex_r5f_initfn(Object *obj) > { > ARMCPU *cpu =3D ARM_CPU(obj); > @@ -1148,6 +1201,7 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { > { .name =3D "cortex-m55", .initfn =3D cortex_m55_initfn, > .class_init =3D arm_v7m_class_init }, > { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, > + { .name =3D "cortex-r52", .initfn =3D cortex_r52_initfn }, > { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, List it below cortex-r5f, so that the two different flavours of R5 stay together. > { .name =3D "ti925t", .initfn =3D ti925t_initfn }, > { .name =3D "sa1100", .initfn =3D sa1100_initfn }, > -- > 2.25.1 > thanks -- PMM