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Fri, 13 May 2022 06:38:11 -0700 (PDT) X-Gm-Message-State: AOAM533rdmhaUl5DIsWxhe7yJ+1B9srkjycwGwP4du4s3eTZTiPkmImX cTgkwfmeLuYTBFk2AJ28DgcGpW2j7GHQYVypr74= X-Google-Smtp-Source: ABdhPJyc6jQ7oXeqwaKeI4M2msfjx940ZJfQsIisC8+jsBLfAcTIu1uk8/qClF49yxMCyO0nT6C2rjU4w4xsSRqqVIM= X-Received: by 2002:a67:ce02:0:b0:32c:f290:a37e with SMTP id s2-20020a67ce02000000b0032cf290a37emr2467373vsl.2.1652449090855; Fri, 13 May 2022 06:38:10 -0700 (PDT) MIME-Version: 1.0 References: <20220511214132.2281431-1-heiko@sntech.de> <20220511214132.2281431-4-heiko@sntech.de> In-Reply-To: From: Guo Ren Date: Fri, 13 May 2022 21:37:59 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 3/3] riscv: implement cache-management errata for T-Head SoCs To: Anup Patel Cc: Heiko Stuebner , Palmer Dabbelt , Paul Walmsley , linux-riscv , "linux-kernel@vger.kernel.org List" , Wei Fu , Atish Patra , Nick Kossifidis , Samuel Holland , Christoph Muellner , Philipp Tomsich , Rob Herring , krzk+dt@kernel.org, DTML X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220513_063814_757745_2C047D21 X-CRM114-Status: GOOD ( 27.73 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Reviewed-by: Guo Ren On Thu, May 12, 2022 at 12:41 PM Anup Patel wrote: > > On Thu, May 12, 2022 at 3:11 AM Heiko Stuebner wrote: > > > > The T-Head C906 and C910 implement a scheme for handling > > cache operations different from the generic Zicbom extension. > > > > Add an errata for it next to the generic dma coherency ops. > > > > Tested-by: Samuel Holland > > Signed-off-by: Heiko Stuebner > > Looks good to me. > > Reviewed-by: Anup Patel > > Regards, > Anup > > > --- > > arch/riscv/Kconfig.erratas | 10 ++++++ > > arch/riscv/errata/thead/errata.c | 5 +++ > > arch/riscv/include/asm/errata_list.h | 47 +++++++++++++++++++++++++--- > > 3 files changed, 58 insertions(+), 4 deletions(-) > > > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > > index ebfcd5cc6eaf..213629bac5d7 100644 > > --- a/arch/riscv/Kconfig.erratas > > +++ b/arch/riscv/Kconfig.erratas > > @@ -54,4 +54,14 @@ config ERRATA_THEAD_PBMT > > > > If you don't know what to do here, say "Y". > > > > +config ERRATA_THEAD_CMO > > + bool "Apply T-Head cache management errata" > > + depends on ERRATA_THEAD && RISCV_ISA_ZICBOM > > + default y > > + help > > + This will apply the cache management errata to handle the > > + non-standard handling on non-coherent operations on T-Head SoCs. > > + > > + If you don't know what to do here, say "Y". > > + > > endmenu > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c > > index e5d75270b99c..9545f43d3504 100644 > > --- a/arch/riscv/errata/thead/errata.c > > +++ b/arch/riscv/errata/thead/errata.c > > @@ -33,6 +33,11 @@ static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = { > > .stage = RISCV_ALTERNATIVES_EARLY_BOOT, > > .check_func = errata_mt_check_func > > }, > > + { > > + .name = "cache-management", > > + .stage = RISCV_ALTERNATIVES_BOOT, > > + .check_func = errata_mt_check_func > > + }, > > }; > > > > static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > > index eebcd4415049..1da311fc5126 100644 > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -16,7 +16,8 @@ > > > > #ifdef CONFIG_ERRATA_THEAD > > #define ERRATA_THEAD_PBMT 0 > > -#define ERRATA_THEAD_NUMBER 1 > > +#define ERRATA_THEAD_CMO 1 > > +#define ERRATA_THEAD_NUMBER 2 > > #endif > > > > #define CPUFEATURE_SVPBMT 0 > > @@ -111,8 +112,37 @@ asm volatile(ALTERNATIVE( \ > > #define CBO_CLEAN_A0 ".long 0x25200F" > > #define CBO_FLUSH_A0 ".long 0x05200F" > > > > +/* > > + * dcache.ipa rs1 (invalidate, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01010 rs1 000 00000 0001011 > > + * dache.iva rs1 (invalida, virtual address) > > + * 0000001 00110 rs1 000 00000 0001011 > > + * > > + * dcache.cpa rs1 (clean, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01001 rs1 000 00000 0001011 > > + * dcache.cva rs1 (clean, virtual address) > > + * 0000001 00100 rs1 000 00000 0001011 > > + * > > + * dcache.cipa rs1 (clean then invalidate, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01011 rs1 000 00000 0001011 > > + * dcache.civa rs1 (... virtual address) > > + * 0000001 00111 rs1 000 00000 0001011 > > + * > > + * sync.s (make sure all cache operations finished) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000000 11001 00000 000 00000 0001011 > > + */ > > +#define THEAD_INVAL_A0 ".long 0x0265000b" > > +#define THEAD_CLEAN_A0 ".long 0x0245000b" > > +#define THEAD_FLUSH_A0 ".long 0x0275000b" > > +#define THEAD_SYNC_S ".long 0x0190000b" > > + > > #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > > -asm volatile(ALTERNATIVE( \ > > +asm volatile(ALTERNATIVE_2( \ > > + "nop\n\t" \ > > "nop\n\t" \ > > "nop\n\t" \ > > "nop\n\t" \ > > @@ -124,8 +154,17 @@ asm volatile(ALTERNATIVE( \ > > CBO_##_op##_A0 "\n\t" \ > > "add a0, a0, %0\n\t" \ > > "2:\n\t" \ > > - "bltu a0, %2, 3b\n\t", 0, \ > > - CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM) \ > > + "bltu a0, %2, 3b\n\t" \ > > + "nop", 0, CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM, \ > > + "mv a0, %1\n\t" \ > > + "j 2f\n\t" \ > > + "3:\n\t" \ > > + THEAD_##_op##_A0 "\n\t" \ > > + "add a0, a0, %0\n\t" \ > > + "2:\n\t" \ > > + "bltu a0, %2, 3b\n\t" \ > > + THEAD_SYNC_S, THEAD_VENDOR_ID, \ > > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > > : : "r"(_cachesize), \ > > "r"(ALIGN((_start), (_cachesize))), \ > > "r"(ALIGN((_start) + (_size), (_cachesize)))) > > -- > > 2.35.1 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C6E2C433EF for ; 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charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Reviewed-by: Guo Ren On Thu, May 12, 2022 at 12:41 PM Anup Patel wrote: > > On Thu, May 12, 2022 at 3:11 AM Heiko Stuebner wrote: > > > > The T-Head C906 and C910 implement a scheme for handling > > cache operations different from the generic Zicbom extension. > > > > Add an errata for it next to the generic dma coherency ops. > > > > Tested-by: Samuel Holland > > Signed-off-by: Heiko Stuebner > > Looks good to me. > > Reviewed-by: Anup Patel > > Regards, > Anup > > > --- > > arch/riscv/Kconfig.erratas | 10 ++++++ > > arch/riscv/errata/thead/errata.c | 5 +++ > > arch/riscv/include/asm/errata_list.h | 47 +++++++++++++++++++++++++--- > > 3 files changed, 58 insertions(+), 4 deletions(-) > > > > diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas > > index ebfcd5cc6eaf..213629bac5d7 100644 > > --- a/arch/riscv/Kconfig.erratas > > +++ b/arch/riscv/Kconfig.erratas > > @@ -54,4 +54,14 @@ config ERRATA_THEAD_PBMT > > > > If you don't know what to do here, say "Y". > > > > +config ERRATA_THEAD_CMO > > + bool "Apply T-Head cache management errata" > > + depends on ERRATA_THEAD && RISCV_ISA_ZICBOM > > + default y > > + help > > + This will apply the cache management errata to handle the > > + non-standard handling on non-coherent operations on T-Head SoCs. > > + > > + If you don't know what to do here, say "Y". > > + > > endmenu > > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c > > index e5d75270b99c..9545f43d3504 100644 > > --- a/arch/riscv/errata/thead/errata.c > > +++ b/arch/riscv/errata/thead/errata.c > > @@ -33,6 +33,11 @@ static const struct errata_info errata_list[ERRATA_THEAD_NUMBER] = { > > .stage = RISCV_ALTERNATIVES_EARLY_BOOT, > > .check_func = errata_mt_check_func > > }, > > + { > > + .name = "cache-management", > > + .stage = RISCV_ALTERNATIVES_BOOT, > > + .check_func = errata_mt_check_func > > + }, > > }; > > > > static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) > > diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h > > index eebcd4415049..1da311fc5126 100644 > > --- a/arch/riscv/include/asm/errata_list.h > > +++ b/arch/riscv/include/asm/errata_list.h > > @@ -16,7 +16,8 @@ > > > > #ifdef CONFIG_ERRATA_THEAD > > #define ERRATA_THEAD_PBMT 0 > > -#define ERRATA_THEAD_NUMBER 1 > > +#define ERRATA_THEAD_CMO 1 > > +#define ERRATA_THEAD_NUMBER 2 > > #endif > > > > #define CPUFEATURE_SVPBMT 0 > > @@ -111,8 +112,37 @@ asm volatile(ALTERNATIVE( \ > > #define CBO_CLEAN_A0 ".long 0x25200F" > > #define CBO_FLUSH_A0 ".long 0x05200F" > > > > +/* > > + * dcache.ipa rs1 (invalidate, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01010 rs1 000 00000 0001011 > > + * dache.iva rs1 (invalida, virtual address) > > + * 0000001 00110 rs1 000 00000 0001011 > > + * > > + * dcache.cpa rs1 (clean, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01001 rs1 000 00000 0001011 > > + * dcache.cva rs1 (clean, virtual address) > > + * 0000001 00100 rs1 000 00000 0001011 > > + * > > + * dcache.cipa rs1 (clean then invalidate, physical address) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000001 01011 rs1 000 00000 0001011 > > + * dcache.civa rs1 (... virtual address) > > + * 0000001 00111 rs1 000 00000 0001011 > > + * > > + * sync.s (make sure all cache operations finished) > > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 | > > + * 0000000 11001 00000 000 00000 0001011 > > + */ > > +#define THEAD_INVAL_A0 ".long 0x0265000b" > > +#define THEAD_CLEAN_A0 ".long 0x0245000b" > > +#define THEAD_FLUSH_A0 ".long 0x0275000b" > > +#define THEAD_SYNC_S ".long 0x0190000b" > > + > > #define ALT_CMO_OP(_op, _start, _size, _cachesize) \ > > -asm volatile(ALTERNATIVE( \ > > +asm volatile(ALTERNATIVE_2( \ > > + "nop\n\t" \ > > "nop\n\t" \ > > "nop\n\t" \ > > "nop\n\t" \ > > @@ -124,8 +154,17 @@ asm volatile(ALTERNATIVE( \ > > CBO_##_op##_A0 "\n\t" \ > > "add a0, a0, %0\n\t" \ > > "2:\n\t" \ > > - "bltu a0, %2, 3b\n\t", 0, \ > > - CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM) \ > > + "bltu a0, %2, 3b\n\t" \ > > + "nop", 0, CPUFEATURE_CMO, CONFIG_RISCV_ISA_ZICBOM, \ > > + "mv a0, %1\n\t" \ > > + "j 2f\n\t" \ > > + "3:\n\t" \ > > + THEAD_##_op##_A0 "\n\t" \ > > + "add a0, a0, %0\n\t" \ > > + "2:\n\t" \ > > + "bltu a0, %2, 3b\n\t" \ > > + THEAD_SYNC_S, THEAD_VENDOR_ID, \ > > + ERRATA_THEAD_CMO, CONFIG_ERRATA_THEAD_CMO) \ > > : : "r"(_cachesize), \ > > "r"(ALIGN((_start), (_cachesize))), \ > > "r"(ALIGN((_start) + (_size), (_cachesize)))) > > -- > > 2.35.1 > > -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/