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Thu, 19 Nov 2020 11:06:42 -0800 (PST) MIME-Version: 1.0 References: <20201118083044.13992-1-frank.chang@sifive.com> <20201118083044.13992-16-frank.chang@sifive.com> In-Reply-To: <20201118083044.13992-16-frank.chang@sifive.com> From: Alistair Francis Date: Thu, 19 Nov 2020 10:54:18 -0800 Message-ID: Subject: Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line To: Frank Chang Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=alistair23@gmail.com; helo=mail-il1-x130.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:RISC-V" , Sagar Karandikar , Bastian Koppelmann , "qemu-devel@nongnu.org Developers" , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Nov 18, 2020 at 12:45 AM wrote: > > From: Kito Cheng > > B-extension is default off, use cpu rv32 or rv64 with x-b=true to > enable B-extension. > > Signed-off-by: Kito Cheng Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 4 ++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f4574..bc29e118c6d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_h) { > target_misa |= RVH; > } > + if (cpu->cfg.ext_b) { > + target_misa |= RVB; > + } > if (cpu->cfg.ext_v) { > target_misa |= RVV; > if (!is_power_of_2(cpu->cfg.vlen)) { > @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de4705bb578..c1c77c58a87 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -66,6 +66,7 @@ > #define RVS RV('S') > #define RVU RV('U') > #define RVH RV('H') > +#define RVB RV('B') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > @@ -278,6 +279,7 @@ struct RISCVCPU { > bool ext_f; > bool ext_d; > bool ext_c; > + bool ext_b; > bool ext_s; > bool ext_u; > bool ext_h; > -- > 2.17.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kfpGZ-0002LY-Ss for mharc-qemu-riscv@gnu.org; Thu, 19 Nov 2020 14:06:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfpGX-0002I1-OL; Thu, 19 Nov 2020 14:06:45 -0500 Received: from mail-il1-x130.google.com ([2607:f8b0:4864:20::130]:33417) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfpGW-0000vx-08; Thu, 19 Nov 2020 14:06:45 -0500 Received: by mail-il1-x130.google.com with SMTP id y9so6375731ilb.0; Thu, 19 Nov 2020 11:06:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5oLmtYiRH6NV6kROXu93cf6redqaxmI04ejhC28b4qA=; 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Thu, 19 Nov 2020 11:06:42 -0800 (PST) MIME-Version: 1.0 References: <20201118083044.13992-1-frank.chang@sifive.com> <20201118083044.13992-16-frank.chang@sifive.com> In-Reply-To: <20201118083044.13992-16-frank.chang@sifive.com> From: Alistair Francis Date: Thu, 19 Nov 2020 10:54:18 -0800 Message-ID: Subject: Re: [RFC 15/15] target/riscv: rvb: support and turn on B-extension from command line To: Frank Chang Cc: "qemu-devel@nongnu.org Developers" , "open list:RISC-V" , Alistair Francis , Kito Cheng , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=alistair23@gmail.com; helo=mail-il1-x130.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Nov 2020 19:06:46 -0000 On Wed, Nov 18, 2020 at 12:45 AM wrote: > > From: Kito Cheng > > B-extension is default off, use cpu rv32 or rv64 with x-b=true to > enable B-extension. > > Signed-off-by: Kito Cheng Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 4 ++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f4574..bc29e118c6d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > if (cpu->cfg.ext_h) { > target_misa |= RVH; > } > + if (cpu->cfg.ext_b) { > + target_misa |= RVB; > + } > if (cpu->cfg.ext_v) { > target_misa |= RVV; > if (!is_power_of_2(cpu->cfg.vlen)) { > @@ -515,6 +518,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, true), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de4705bb578..c1c77c58a87 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -66,6 +66,7 @@ > #define RVS RV('S') > #define RVU RV('U') > #define RVH RV('H') > +#define RVB RV('B') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > @@ -278,6 +279,7 @@ struct RISCVCPU { > bool ext_f; > bool ext_d; > bool ext_c; > + bool ext_b; > bool ext_s; > bool ext_u; > bool ext_h; > -- > 2.17.1 > >