diff for duplicates of <CAMSpPPfOwnevUNui+zUe1bbq655kHQ=u3FyOiRTO5NAo0yWBTg@mail.gmail.com>
diff --git a/a/1.txt b/N1/1.txt
index e4fcf2b..d90d40b 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,12 +1,18 @@
On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza <oza.oza@broadcom.com> wrote:
-> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
+> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas <helgaas@kernel.org> wrote=
+:
>> On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:
->>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas <helgaas@kernel.org> wrote:
+>>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas <helgaas@kernel.org> wrot=
+e:
>>> > On Thu, Jul 06, 2017 at 08:39:41AM +0530, Oza Pawandeep wrote:
->>> >> For Configuration Requests only, following reset it is possible for a
->>> >> device to terminate the request but indicate that it is temporarily unable
->>> >> to process the Request, but will be able to process the Request in the
->>> >> future – in this case, the Configuration Request Retry Status 100 (CRS)
+>>> >> For Configuration Requests only, following reset it is possible for =
+a
+>>> >> device to terminate the request but indicate that it is temporarily =
+unable
+>>> >> to process the Request, but will be able to process the Request in t=
+he
+>>> >> future =E2=80=93 in this case, the Configuration Request Retry Statu=
+s 100 (CRS)
>>> >> Completion Status is used.
>>> >
>>> > Please include the spec reference for this.
@@ -20,7 +26,8 @@ On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza <oza.oza@broadcom.com> wrote:
>>>
>>> I will remove the above description from the comment.
>>>
->>> >> As per PCI spec, CRS Software Visibility only affects config read of the
+>>> >> As per PCI spec, CRS Software Visibility only affects config read of=
+ the
>>> >> Vendor ID, for config write or any other config read the Root must
>>> >> automatically re-issue configuration request again as a new request.
>>> >> Iproc based PCIe RC (hw) does not retry request on its own.
@@ -28,7 +35,8 @@ On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza <oza.oza@broadcom.com> wrote:
>>> > I think sec 2.3.2 is the relevant part of the spec. It basically
>>> > says that when an RC receives a CRS completion for a config request:
>>> >
->>> > - If CRS software visibility is not enabled, the RC must reissue the
+>>> > - If CRS software visibility is not enabled, the RC must reissue th=
+e
>>> > config request as a new request.
>>> >
>>> > - If CRS software visibility is enabled,
@@ -87,7 +95,8 @@ now above those 2 registers are implemented by host bridge (not in
PCIe core IP).
there is no way of knowing for software, if write has to be retried.
-e.g. I can not read data register (step B) to check if write was successful.
+e.g. I can not read data register (step B) to check if write was successful=
+.
I have double checked this with internal ASIC team here.
so in conclusion: I have to do following of things.
@@ -112,23 +121,26 @@ Oza.
>>> cycles. In this case, the RC needs to re-issue the request. The IP
>>> does not handle this because the number of configuration cycles needed
>>> will probably be less
->>> than the total number of non-posted operations needed. When a retry status
+>>> than the total number of non-posted operations needed. When a retry s=
+tatus
>>> is received on the User RX interface for a configuration request that
>>> was sent on the User TX interface, it will be indicated with a
->>> completion with the CMPL_STATUS field set to 2=CRS, and the user will
+>>> completion with the CMPL_STATUS field set to 2=3DCRS, and the user will
>>> have to find the address and data values and send a new transaction on
>>> the User TX interface.
>>> When the internal configuration space returns a retry status during a
->>> configuration cycle (user_cscfg = 1) on the Command/Status interface,
+>>> configuration cycle (user_cscfg =3D 1) on the Command/Status interface,
>>> the pcie_cscrs will assert with the pcie_csack signal to indicate the
>>> CRS status.
>>> When the CRS Software Visibility Enable register in the Root Control
>>> register is enabled, the IP will return the data value to 0x0001 for
->>> the Vendor ID value and 0xffff (all 1’s) for the rest of the data in
+>>> the Vendor ID value and 0xffff (all 1=E2=80=99s) for the rest of the d=
+ata in
>>> the request for reads of offset 0 that return with CRS status. This
>>> is true for both the User RX Interface and for the Command/Status
>>> interface. When CRS Software Visibility is enabled, the CMPL_STATUS
->>> field of the completion on the User RX Interface will not be 2=CRS and
+>>> field of the completion on the User RX Interface will not be 2=3DCRS an=
+d
>>> the pcie_cscrs signal will not assert on the Command/Status interface.
>>> >>
>>> Broadcom does not sell PCIe core IP, so above information is not
@@ -136,8 +148,10 @@ Oza.
>>>
>>>
>>> >
->>> >> As a result of the fact, PCIe RC driver (sw) should take care of CRS.
->>> >> This patch fixes the problem, and attempts to read config space again in
+>>> >> As a result of the fact, PCIe RC driver (sw) should take care of CRS=
+.
+>>> >> This patch fixes the problem, and attempts to read config space agai=
+n in
>>> >> case of PCIe code forwarding the CRS back to CPU.
>>> >> It implements iproc_pcie_config_read which gets called for Stingray,
>>> >> Otherwise it falls back to PCI generic APIs.
@@ -146,7 +160,8 @@ Oza.
>>> >> Reviewed-by: Ray Jui <ray.jui@broadcom.com>
>>> >> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
>>> >>
->>> >> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
+>>> >> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-i=
+proc.c
>>> >> index 0f39bd2..b0abcd7 100644
>>> >> --- a/drivers/pci/host/pcie-iproc.c
>>> >> +++ b/drivers/pci/host/pcie-iproc.c
@@ -155,18 +170,21 @@ Oza.
>>> >> #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
>>> >>
>>> >> +#define CFG_RETRY_STATUS 0xffff0001
->>> >> +#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milli-seconds. */
+>>> >> +#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milli-seconds. *=
+/
>>> >> +
->>> >> /* derive the enum index of the outbound/inbound mapping registers */
+>>> >> /* derive the enum index of the outbound/inbound mapping registers =
+*/
>>> >> #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
>>> >>
->>> >> @@ -448,6 +451,55 @@ static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
+>>> >> @@ -448,6 +451,55 @@ static inline void iproc_pcie_apb_err_disable(s=
+truct pci_bus *bus,
>>> >> }
>>> >> }
>>> >>
>>> >> +static int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
>>> >> +{
->>> >> + int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
+>>> >> + int timeout =3D CFG_RETRY_STATUS_TIMEOUT_US;
>>> >> + unsigned int ret;
>>> >> +
>>> >> + /*
@@ -178,8 +196,8 @@ Oza.
>>> >> + * request on its own, so handle it here.
>>> >> + */
>>> >> + do {
->>> >> + ret = readl(cfg_data_p);
->>> >> + if (ret == CFG_RETRY_STATUS)
+>>> >> + ret =3D readl(cfg_data_p);
+>>> >> + if (ret =3D=3D CFG_RETRY_STATUS)
>>> >> + udelay(1);
>>> >> + else
>>> >> + return PCIBIOS_SUCCESSFUL;
@@ -212,7 +230,8 @@ Oza.
> such that this data is unlikely to be valid.
>
> however I have found one case where this data is valid.
-> which is; BAR exposing 64-bit IO memory, which seems legacy and is rare as well.
+> which is; BAR exposing 64-bit IO memory, which seems legacy and is rare a=
+s well.
>
> however in our next chip revision, ASIC will give us separate CRS
> register in our host-bridge.
@@ -236,10 +255,12 @@ Oza.
>
>>
>>> > If CRS software visibility is enabled, we should return the 0x0001
->>> > data if we're reading the Vendor ID and see CRS status. It looks like
+>>> > data if we're reading the Vendor ID and see CRS status. It looks lik=
+e
>>> > this loop always retries if we see 0xffff0001 data.
>>> >
->>> our internal host bridge is implemented this way, and it returns 0xffff0001.
+>>> our internal host bridge is implemented this way, and it returns 0xffff=
+0001.
>>> so there, we have no choice.
>>
>> The PCIe spec says that if CRS software visibility is enabled and we
@@ -287,7 +308,8 @@ Oza.
>>> >> + return PCIBIOS_DEVICE_NOT_FOUND;
>>> >> +}
>>> >> +
->>> >> +static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
+>>> >> +static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *p=
+cie,
>>> >> + unsigned int busno,
>>> >> + unsigned int slot,
>>> >> + unsigned int fn,
@@ -297,14 +319,14 @@ Oza.
>>> >> + u32 val;
>>> >> +
>>> >> + /* EP device access */
->>> >> + val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
+>>> >> + val =3D (busno << CFG_ADDR_BUS_NUM_SHIFT) |
>>> >> + (slot << CFG_ADDR_DEV_NUM_SHIFT) |
>>> >> + (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
>>> >> + (where & CFG_ADDR_REG_NUM_MASK) |
>>> >> + (1 & CFG_ADDR_CFG_TYPE_MASK);
>>> >> +
>>> >> + iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
->>> >> + offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
+>>> >> + offset =3D iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
>>> >> +
>>> >> + if (iproc_pcie_reg_is_invalid(offset))
>>> >> + return NULL;
@@ -313,55 +335,65 @@ Oza.
>>> >> +}
>>> >> +
>>> >> /**
->>> >> * Note access to the configuration registers are protected at the higher layer
+>>> >> * Note access to the configuration registers are protected at the =
+higher layer
>>> >> * by 'pci_lock' in drivers/pci/access.c
->>> >> @@ -499,13 +551,48 @@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,
+>>> >> @@ -499,13 +551,48 @@ static void __iomem *iproc_pcie_map_cfg_bus(st=
+ruct pci_bus *bus,
>>> >> return (pcie->base + offset);
>>> >> }
>>> >>
->>> >> +static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
+>>> >> +static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int=
+ devfn,
>>> >> + int where, int size, u32 *val)
>>> >> +{
->>> >> + struct iproc_pcie *pcie = iproc_data(bus);
->>> >> + unsigned int slot = PCI_SLOT(devfn);
->>> >> + unsigned int fn = PCI_FUNC(devfn);
->>> >> + unsigned int busno = bus->number;
+>>> >> + struct iproc_pcie *pcie =3D iproc_data(bus);
+>>> >> + unsigned int slot =3D PCI_SLOT(devfn);
+>>> >> + unsigned int fn =3D PCI_FUNC(devfn);
+>>> >> + unsigned int busno =3D bus->number;
>>> >> + void __iomem *cfg_data_p;
>>> >> + int ret;
>>> >> +
>>> >> + /* root complex access. */
->>> >> + if (busno == 0)
->>> >> + return pci_generic_config_read32(bus, devfn, where, size, val);
+>>> >> + if (busno =3D=3D 0)
+>>> >> + return pci_generic_config_read32(bus, devfn, where, si=
+ze, val);
>>> >> +
->>> >> + cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
+>>> >> + cfg_data_p =3D iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn=
+, where);
>>> >> +
>>> >> + if (!cfg_data_p)
>>> >> + return PCIBIOS_DEVICE_NOT_FOUND;
>>> >> +
->>> >> + ret = iproc_pcie_cfg_retry(cfg_data_p);
+>>> >> + ret =3D iproc_pcie_cfg_retry(cfg_data_p);
>>> >> + if (ret)
>>> >> + return ret;
>>> >> +
->>> >> + *val = readl(cfg_data_p);
+>>> >> + *val =3D readl(cfg_data_p);
>>> >> +
->>> >> + if (size <= 2)
->>> >> + *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+>>> >> + if (size <=3D 2)
+>>> >> + *val =3D (*val >> (8 * (where & 3))) & ((1 << (size * =
+8)) - 1);
>>> >> +
>>> >> + return PCIBIOS_SUCCESSFUL;
>>> >> +}
>>> >> +
->>> >> static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
+>>> >> static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned i=
+nt devfn,
>>> >> int where, int size, u32 *val)
>>> >> {
>>> >> int ret;
->>> >> + struct iproc_pcie *pcie = iproc_data(bus);
+>>> >> + struct iproc_pcie *pcie =3D iproc_data(bus);
>>> >>
>>> >> iproc_pcie_apb_err_disable(bus, true);
->>> >> - ret = pci_generic_config_read32(bus, devfn, where, size, val);
->>> >> + if (pcie->type == IPROC_PCIE_PAXB_V2)
->>> >> + ret = iproc_pcie_config_read(bus, devfn, where, size, val);
+>>> >> - ret =3D pci_generic_config_read32(bus, devfn, where, size, val=
+);
+>>> >> + if (pcie->type =3D=3D IPROC_PCIE_PAXB_V2)
+>>> >> + ret =3D iproc_pcie_config_read(bus, devfn, where, size=
+, val);
>>> >> + else
->>> >> + ret = pci_generic_config_read32(bus, devfn, where, size, val);
+>>> >> + ret =3D pci_generic_config_read32(bus, devfn, where, s=
+ize, val);
>>> >> iproc_pcie_apb_err_disable(bus, false);
>>> >>
>>> >> return ret;
diff --git a/a/content_digest b/N1/content_digest
index 29ace47..0f2d709 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -47,14 +47,20 @@
]
[
"On Fri, Aug 4, 2017 at 11:29 AM, Oza Oza <oza.oza\@broadcom.com> wrote:\n",
- "> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas <helgaas\@kernel.org> wrote:\n",
+ "> On Fri, Aug 4, 2017 at 12:27 AM, Bjorn Helgaas <helgaas\@kernel.org> wrote=\n",
+ ":\n",
">> On Thu, Aug 03, 2017 at 01:50:29PM +0530, Oza Oza wrote:\n",
- ">>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas <helgaas\@kernel.org> wrote:\n",
+ ">>> On Thu, Aug 3, 2017 at 2:34 AM, Bjorn Helgaas <helgaas\@kernel.org> wrot=\n",
+ "e:\n",
">>> > On Thu, Jul 06, 2017 at 08:39:41AM +0530, Oza Pawandeep wrote:\n",
- ">>> >> For Configuration Requests only, following reset it is possible for a\n",
- ">>> >> device to terminate the request but indicate that it is temporarily unable\n",
- ">>> >> to process the Request, but will be able to process the Request in the\n",
- ">>> >> future \342\200\223 in this case, the Configuration Request Retry Status 100 (CRS)\n",
+ ">>> >> For Configuration Requests only, following reset it is possible for =\n",
+ "a\n",
+ ">>> >> device to terminate the request but indicate that it is temporarily =\n",
+ "unable\n",
+ ">>> >> to process the Request, but will be able to process the Request in t=\n",
+ "he\n",
+ ">>> >> future =E2=80=93 in this case, the Configuration Request Retry Statu=\n",
+ "s 100 (CRS)\n",
">>> >> Completion Status is used.\n",
">>> >\n",
">>> > Please include the spec reference for this.\n",
@@ -68,7 +74,8 @@
">>>\n",
">>> I will remove the above description from the comment.\n",
">>>\n",
- ">>> >> As per PCI spec, CRS Software Visibility only affects config read of the\n",
+ ">>> >> As per PCI spec, CRS Software Visibility only affects config read of=\n",
+ " the\n",
">>> >> Vendor ID, for config write or any other config read the Root must\n",
">>> >> automatically re-issue configuration request again as a new request.\n",
">>> >> Iproc based PCIe RC (hw) does not retry request on its own.\n",
@@ -76,7 +83,8 @@
">>> > I think sec 2.3.2 is the relevant part of the spec. It basically\n",
">>> > says that when an RC receives a CRS completion for a config request:\n",
">>> >\n",
- ">>> > - If CRS software visibility is not enabled, the RC must reissue the\n",
+ ">>> > - If CRS software visibility is not enabled, the RC must reissue th=\n",
+ "e\n",
">>> > config request as a new request.\n",
">>> >\n",
">>> > - If CRS software visibility is enabled,\n",
@@ -135,7 +143,8 @@
"PCIe core IP).\n",
"there is no way of knowing for software, if write has to be retried.\n",
"\n",
- "e.g. I can not read data register (step B) to check if write was successful.\n",
+ "e.g. I can not read data register (step B) to check if write was successful=\n",
+ ".\n",
"I have double checked this with internal ASIC team here.\n",
"\n",
"so in conclusion: I have to do following of things.\n",
@@ -160,23 +169,26 @@
">>> cycles. In this case, the RC needs to re-issue the request. The IP\n",
">>> does not handle this because the number of configuration cycles needed\n",
">>> will probably be less\n",
- ">>> than the total number of non-posted operations needed. When a retry status\n",
+ ">>> than the total number of non-posted operations needed. When a retry s=\n",
+ "tatus\n",
">>> is received on the User RX interface for a configuration request that\n",
">>> was sent on the User TX interface, it will be indicated with a\n",
- ">>> completion with the CMPL_STATUS field set to 2=CRS, and the user will\n",
+ ">>> completion with the CMPL_STATUS field set to 2=3DCRS, and the user will\n",
">>> have to find the address and data values and send a new transaction on\n",
">>> the User TX interface.\n",
">>> When the internal configuration space returns a retry status during a\n",
- ">>> configuration cycle (user_cscfg = 1) on the Command/Status interface,\n",
+ ">>> configuration cycle (user_cscfg =3D 1) on the Command/Status interface,\n",
">>> the pcie_cscrs will assert with the pcie_csack signal to indicate the\n",
">>> CRS status.\n",
">>> When the CRS Software Visibility Enable register in the Root Control\n",
">>> register is enabled, the IP will return the data value to 0x0001 for\n",
- ">>> the Vendor ID value and 0xffff (all 1\342\200\231s) for the rest of the data in\n",
+ ">>> the Vendor ID value and 0xffff (all 1=E2=80=99s) for the rest of the d=\n",
+ "ata in\n",
">>> the request for reads of offset 0 that return with CRS status. This\n",
">>> is true for both the User RX Interface and for the Command/Status\n",
">>> interface. When CRS Software Visibility is enabled, the CMPL_STATUS\n",
- ">>> field of the completion on the User RX Interface will not be 2=CRS and\n",
+ ">>> field of the completion on the User RX Interface will not be 2=3DCRS an=\n",
+ "d\n",
">>> the pcie_cscrs signal will not assert on the Command/Status interface.\n",
">>> >>\n",
">>> Broadcom does not sell PCIe core IP, so above information is not\n",
@@ -184,8 +196,10 @@
">>>\n",
">>>\n",
">>> >\n",
- ">>> >> As a result of the fact, PCIe RC driver (sw) should take care of CRS.\n",
- ">>> >> This patch fixes the problem, and attempts to read config space again in\n",
+ ">>> >> As a result of the fact, PCIe RC driver (sw) should take care of CRS=\n",
+ ".\n",
+ ">>> >> This patch fixes the problem, and attempts to read config space agai=\n",
+ "n in\n",
">>> >> case of PCIe code forwarding the CRS back to CPU.\n",
">>> >> It implements iproc_pcie_config_read which gets called for Stingray,\n",
">>> >> Otherwise it falls back to PCI generic APIs.\n",
@@ -194,7 +208,8 @@
">>> >> Reviewed-by: Ray Jui <ray.jui\@broadcom.com>\n",
">>> >> Reviewed-by: Scott Branden <scott.branden\@broadcom.com>\n",
">>> >>\n",
- ">>> >> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c\n",
+ ">>> >> diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-i=\n",
+ "proc.c\n",
">>> >> index 0f39bd2..b0abcd7 100644\n",
">>> >> --- a/drivers/pci/host/pcie-iproc.c\n",
">>> >> +++ b/drivers/pci/host/pcie-iproc.c\n",
@@ -203,18 +218,21 @@
">>> >> #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)\n",
">>> >>\n",
">>> >> +#define CFG_RETRY_STATUS 0xffff0001\n",
- ">>> >> +#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milli-seconds. */\n",
+ ">>> >> +#define CFG_RETRY_STATUS_TIMEOUT_US 500000 /* 500 milli-seconds. *=\n",
+ "/\n",
">>> >> +\n",
- ">>> >> /* derive the enum index of the outbound/inbound mapping registers */\n",
+ ">>> >> /* derive the enum index of the outbound/inbound mapping registers =\n",
+ "*/\n",
">>> >> #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)\n",
">>> >>\n",
- ">>> >> \@\@ -448,6 +451,55 \@\@ static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,\n",
+ ">>> >> \@\@ -448,6 +451,55 \@\@ static inline void iproc_pcie_apb_err_disable(s=\n",
+ "truct pci_bus *bus,\n",
">>> >> }\n",
">>> >> }\n",
">>> >>\n",
">>> >> +static int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)\n",
">>> >> +{\n",
- ">>> >> + int timeout = CFG_RETRY_STATUS_TIMEOUT_US;\n",
+ ">>> >> + int timeout =3D CFG_RETRY_STATUS_TIMEOUT_US;\n",
">>> >> + unsigned int ret;\n",
">>> >> +\n",
">>> >> + /*\n",
@@ -226,8 +244,8 @@
">>> >> + * request on its own, so handle it here.\n",
">>> >> + */\n",
">>> >> + do {\n",
- ">>> >> + ret = readl(cfg_data_p);\n",
- ">>> >> + if (ret == CFG_RETRY_STATUS)\n",
+ ">>> >> + ret =3D readl(cfg_data_p);\n",
+ ">>> >> + if (ret =3D=3D CFG_RETRY_STATUS)\n",
">>> >> + udelay(1);\n",
">>> >> + else\n",
">>> >> + return PCIBIOS_SUCCESSFUL;\n",
@@ -260,7 +278,8 @@
"> such that this data is unlikely to be valid.\n",
">\n",
"> however I have found one case where this data is valid.\n",
- "> which is; BAR exposing 64-bit IO memory, which seems legacy and is rare as well.\n",
+ "> which is; BAR exposing 64-bit IO memory, which seems legacy and is rare a=\n",
+ "s well.\n",
">\n",
"> however in our next chip revision, ASIC will give us separate CRS\n",
"> register in our host-bridge.\n",
@@ -284,10 +303,12 @@
">\n",
">>\n",
">>> > If CRS software visibility is enabled, we should return the 0x0001\n",
- ">>> > data if we're reading the Vendor ID and see CRS status. It looks like\n",
+ ">>> > data if we're reading the Vendor ID and see CRS status. It looks lik=\n",
+ "e\n",
">>> > this loop always retries if we see 0xffff0001 data.\n",
">>> >\n",
- ">>> our internal host bridge is implemented this way, and it returns 0xffff0001.\n",
+ ">>> our internal host bridge is implemented this way, and it returns 0xffff=\n",
+ "0001.\n",
">>> so there, we have no choice.\n",
">>\n",
">> The PCIe spec says that if CRS software visibility is enabled and we\n",
@@ -335,7 +356,8 @@
">>> >> + return PCIBIOS_DEVICE_NOT_FOUND;\n",
">>> >> +}\n",
">>> >> +\n",
- ">>> >> +static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,\n",
+ ">>> >> +static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *p=\n",
+ "cie,\n",
">>> >> + unsigned int busno,\n",
">>> >> + unsigned int slot,\n",
">>> >> + unsigned int fn,\n",
@@ -345,14 +367,14 @@
">>> >> + u32 val;\n",
">>> >> +\n",
">>> >> + /* EP device access */\n",
- ">>> >> + val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |\n",
+ ">>> >> + val =3D (busno << CFG_ADDR_BUS_NUM_SHIFT) |\n",
">>> >> + (slot << CFG_ADDR_DEV_NUM_SHIFT) |\n",
">>> >> + (fn << CFG_ADDR_FUNC_NUM_SHIFT) |\n",
">>> >> + (where & CFG_ADDR_REG_NUM_MASK) |\n",
">>> >> + (1 & CFG_ADDR_CFG_TYPE_MASK);\n",
">>> >> +\n",
">>> >> + iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);\n",
- ">>> >> + offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);\n",
+ ">>> >> + offset =3D iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);\n",
">>> >> +\n",
">>> >> + if (iproc_pcie_reg_is_invalid(offset))\n",
">>> >> + return NULL;\n",
@@ -361,55 +383,65 @@
">>> >> +}\n",
">>> >> +\n",
">>> >> /**\n",
- ">>> >> * Note access to the configuration registers are protected at the higher layer\n",
+ ">>> >> * Note access to the configuration registers are protected at the =\n",
+ "higher layer\n",
">>> >> * by 'pci_lock' in drivers/pci/access.c\n",
- ">>> >> \@\@ -499,13 +551,48 \@\@ static void __iomem *iproc_pcie_map_cfg_bus(struct pci_bus *bus,\n",
+ ">>> >> \@\@ -499,13 +551,48 \@\@ static void __iomem *iproc_pcie_map_cfg_bus(st=\n",
+ "ruct pci_bus *bus,\n",
">>> >> return (pcie->base + offset);\n",
">>> >> }\n",
">>> >>\n",
- ">>> >> +static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,\n",
+ ">>> >> +static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int=\n",
+ " devfn,\n",
">>> >> + int where, int size, u32 *val)\n",
">>> >> +{\n",
- ">>> >> + struct iproc_pcie *pcie = iproc_data(bus);\n",
- ">>> >> + unsigned int slot = PCI_SLOT(devfn);\n",
- ">>> >> + unsigned int fn = PCI_FUNC(devfn);\n",
- ">>> >> + unsigned int busno = bus->number;\n",
+ ">>> >> + struct iproc_pcie *pcie =3D iproc_data(bus);\n",
+ ">>> >> + unsigned int slot =3D PCI_SLOT(devfn);\n",
+ ">>> >> + unsigned int fn =3D PCI_FUNC(devfn);\n",
+ ">>> >> + unsigned int busno =3D bus->number;\n",
">>> >> + void __iomem *cfg_data_p;\n",
">>> >> + int ret;\n",
">>> >> +\n",
">>> >> + /* root complex access. */\n",
- ">>> >> + if (busno == 0)\n",
- ">>> >> + return pci_generic_config_read32(bus, devfn, where, size, val);\n",
+ ">>> >> + if (busno =3D=3D 0)\n",
+ ">>> >> + return pci_generic_config_read32(bus, devfn, where, si=\n",
+ "ze, val);\n",
">>> >> +\n",
- ">>> >> + cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);\n",
+ ">>> >> + cfg_data_p =3D iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn=\n",
+ ", where);\n",
">>> >> +\n",
">>> >> + if (!cfg_data_p)\n",
">>> >> + return PCIBIOS_DEVICE_NOT_FOUND;\n",
">>> >> +\n",
- ">>> >> + ret = iproc_pcie_cfg_retry(cfg_data_p);\n",
+ ">>> >> + ret =3D iproc_pcie_cfg_retry(cfg_data_p);\n",
">>> >> + if (ret)\n",
">>> >> + return ret;\n",
">>> >> +\n",
- ">>> >> + *val = readl(cfg_data_p);\n",
+ ">>> >> + *val =3D readl(cfg_data_p);\n",
">>> >> +\n",
- ">>> >> + if (size <= 2)\n",
- ">>> >> + *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);\n",
+ ">>> >> + if (size <=3D 2)\n",
+ ">>> >> + *val =3D (*val >> (8 * (where & 3))) & ((1 << (size * =\n",
+ "8)) - 1);\n",
">>> >> +\n",
">>> >> + return PCIBIOS_SUCCESSFUL;\n",
">>> >> +}\n",
">>> >> +\n",
- ">>> >> static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,\n",
+ ">>> >> static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned i=\n",
+ "nt devfn,\n",
">>> >> int where, int size, u32 *val)\n",
">>> >> {\n",
">>> >> int ret;\n",
- ">>> >> + struct iproc_pcie *pcie = iproc_data(bus);\n",
+ ">>> >> + struct iproc_pcie *pcie =3D iproc_data(bus);\n",
">>> >>\n",
">>> >> iproc_pcie_apb_err_disable(bus, true);\n",
- ">>> >> - ret = pci_generic_config_read32(bus, devfn, where, size, val);\n",
- ">>> >> + if (pcie->type == IPROC_PCIE_PAXB_V2)\n",
- ">>> >> + ret = iproc_pcie_config_read(bus, devfn, where, size, val);\n",
+ ">>> >> - ret =3D pci_generic_config_read32(bus, devfn, where, size, val=\n",
+ ");\n",
+ ">>> >> + if (pcie->type =3D=3D IPROC_PCIE_PAXB_V2)\n",
+ ">>> >> + ret =3D iproc_pcie_config_read(bus, devfn, where, size=\n",
+ ", val);\n",
">>> >> + else\n",
- ">>> >> + ret = pci_generic_config_read32(bus, devfn, where, size, val);\n",
+ ">>> >> + ret =3D pci_generic_config_read32(bus, devfn, where, s=\n",
+ "ize, val);\n",
">>> >> iproc_pcie_apb_err_disable(bus, false);\n",
">>> >>\n",
">>> >> return ret;\n",
@@ -418,4 +450,4 @@
">>> >>"
]
-f7d64852ff3cd7576e36ae5bf694761fe7a317a6213dbcb817c8243b6768a706
+fb89b5dad764a8109c5c6dc6bcca5604dc3197dd7f6a07e2ea99ac5a846c66e8
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