Re: [PATCH v2 3/5] pinctrl: renesas: pinctrl-rzg2l: Add support to get/set pin config for GPIO port pins

From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v2 3/5] pinctrl: renesas: pinctrl-rzg2l: Add support to get/set pin config for GPIO port pins
Date: Tue, 9 Nov 2021 16:00:03 +0100	[thread overview]
Message-ID: <CAMuHMdW8NeSpv35a7Eq_+NMAE5Uamm_pD+Dp+OeHvCMqd3f2Xw@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8t2KZNqCHJQP_bj9+-RKVBBJpz=pnBXzpyy4tjbUe14EA@mail.gmail.com>

Hi Prabhakar,

On Tue, Nov 9, 2021 at 3:31 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Nov 8, 2021 at 3:36 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, Oct 29, 2021 at 2:44 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Add support to get/set pin config for GPIO port pins.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >
> > > @@ -495,6 +512,14 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
> > >                 port = RZG2L_SINGLE_PIN_GET_PORT(*pin_data);
> > >                 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data);
> > >                 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
> > > +       } else {
> > > +               cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data);
> > > +               port = RZG2L_PIN_ID_TO_PORT(_pin);
> > > +               bit = RZG2L_PIN_ID_TO_PIN(_pin);
> > > +               port_pin = true;
> >
> > Instead of setting this flag, perhaps port should be adjusted?
>
> Something like below?
>
> #define RZG2L_PORT_START_OFFSET 0x10
>
> port = RZG2L_PIN_ID_TO_PORT_pin) + RZG2L_PORT_START_OFFSET;
> rzg2l_validate_gpio_pin(pctrl, *pin_data, port - RZG2L_PORT_START_OFFSET, bit)

Or adjust port after the call to rzg2l_validate_gpio_pin(), to avoid adding
the offset first, and subtracting it again for calling the latter?

> and rename port -> port_offset in rzg2l_pinctrl_pinconf_get/set

That makes sense.  Currently "port" has two meanings: it can mean
either the GPIO port index, or the global register index covering both
single function pin groups and GPIO port indices.
RZG2L_SINGLE_PIN_GET_PORT() returns the latter.
RZG2L_PIN_ID_TO_PORT() returns the former, thus needing an extra offset
to convert to the global register index.

> Or
> would you prefer to change the RZG2L_PIN_ID_TO_PORT macro and adjust
> the entire file?

Changing RZG2L_PIN_ID_TO_PORT() would imply changing all macros
accessing GPIO registers, and is thus quite intrusive.

> > Then rzg2l_r{ead,mw}_pin_config() don't have to care about that
> > anymore.
> >
> Agreed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds