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From: Greg Bellows <greg.bellows@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Andrew Jones" <drjones@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"QEMU Developers" <qemu-devel@nongnu.org>,
	"Patch Tracking" <patches@linaro.org>
Subject: Re: [Qemu-devel] [PATCH 10/11] target-arm: Reindent ancient page-table-walk code
Date: Mon, 26 Jan 2015 16:53:52 -0600	[thread overview]
Message-ID: <CAOgzsHUU2gjuY-P8KyUB+xm+Djtw0KkacqzvojpAP0Vs7NF8aA@mail.gmail.com> (raw)
In-Reply-To: <1422037228-5363-11-git-send-email-peter.maydell@linaro.org>

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On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> A few of the oldest parts of the page-table-walk code have broken indent
> (either hardcoded tabs or two-spaces). Reindent these sections.
>
> For ease of review, this patch does not touch the brace style and
> so is a whitespace-only change.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/helper.c | 192
> ++++++++++++++++++++++++++--------------------------
>  1 file changed, 96 insertions(+), 96 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 0a06bbe..3a23af8 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4636,55 +4636,55 @@ static inline int check_ap(CPUARMState *env,
> ARMMMUIdx mmu_idx,
>                             int ap, int domain_prot,
>                             int access_type)
>  {
> -  int prot_ro;
> -  bool is_user = regime_is_user(env, mmu_idx);
> -
> -  if (domain_prot == 3) {
> -    return PAGE_READ | PAGE_WRITE;
> -  }
> -
> -  if (access_type == 1)
> -      prot_ro = 0;
> -  else
> -      prot_ro = PAGE_READ;
> -
> -  switch (ap) {
> -  case 0:
> -      if (arm_feature(env, ARM_FEATURE_V7)) {
> -          return 0;
> -      }
> -      if (access_type == 1)
> -          return 0;
> -      switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
> -      case SCTLR_S:
> -          return is_user ? 0 : PAGE_READ;
> -      case SCTLR_R:
> -          return PAGE_READ;
> -      default:
> -          return 0;
> -      }
> -  case 1:
> -      return is_user ? 0 : PAGE_READ | PAGE_WRITE;
> -  case 2:
> -      if (is_user)
> -          return prot_ro;
> -      else
> -          return PAGE_READ | PAGE_WRITE;
> -  case 3:
> -      return PAGE_READ | PAGE_WRITE;
> -  case 4: /* Reserved.  */
> -      return 0;
> -  case 5:
> -      return is_user ? 0 : prot_ro;
> -  case 6:
> -      return prot_ro;
> -  case 7:
> -      if (!arm_feature (env, ARM_FEATURE_V6K))
> -          return 0;
> -      return prot_ro;
> -  default:
> -      abort();
> -  }
> +    int prot_ro;
> +    bool is_user = regime_is_user(env, mmu_idx);
> +
> +    if (domain_prot == 3) {
> +        return PAGE_READ | PAGE_WRITE;
> +    }
> +
> +    if (access_type == 1)
> +        prot_ro = 0;
> +    else
> +        prot_ro = PAGE_READ;
> +
> +    switch (ap) {
> +    case 0:
> +        if (arm_feature(env, ARM_FEATURE_V7)) {
> +            return 0;
> +        }
> +        if (access_type == 1)
> +            return 0;
> +        switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
> +        case SCTLR_S:
> +            return is_user ? 0 : PAGE_READ;
> +        case SCTLR_R:
> +            return PAGE_READ;
> +        default:
> +            return 0;
> +        }
> +    case 1:
> +        return is_user ? 0 : PAGE_READ | PAGE_WRITE;
> +    case 2:
> +        if (is_user)
> +            return prot_ro;
> +        else
> +            return PAGE_READ | PAGE_WRITE;
> +    case 3:
> +        return PAGE_READ | PAGE_WRITE;
> +    case 4: /* Reserved.  */
> +        return 0;
> +    case 5:
> +        return is_user ? 0 : prot_ro;
> +    case 6:
> +        return prot_ro;
> +    case 7:
> +        if (!arm_feature (env, ARM_FEATURE_V6K))
> +            return 0;
> +        return prot_ro;
> +    default:
> +        abort();
> +    }
>  }
>
>  static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
> @@ -4762,13 +4762,13 @@ static int get_phys_addr_v5(CPUARMState *env,
> uint32_t address, int access_type,
>          *page_size = 1024 * 1024;
>      } else {
>          /* Lookup l2 entry.  */
> -       if (type == 1) {
> -           /* Coarse pagetable.  */
> -           table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
> -       } else {
> -           /* Fine pagetable.  */
> -           table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
> -       }
> +        if (type == 1) {
> +            /* Coarse pagetable.  */
> +            table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
> +        } else {
> +            /* Fine pagetable.  */
> +            table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
> +        }
>          desc = ldl_phys(cs->as, table);
>          switch (desc & 3) {
>          case 0: /* Page translation fault.  */
> @@ -4785,17 +4785,17 @@ static int get_phys_addr_v5(CPUARMState *env,
> uint32_t address, int access_type,
>              *page_size = 0x1000;
>              break;
>          case 3: /* 1k page.  */
> -           if (type == 1) {
> -               if (arm_feature(env, ARM_FEATURE_XSCALE)) {
> -                   phys_addr = (desc & 0xfffff000) | (address & 0xfff);
> -               } else {
> -                   /* Page translation fault.  */
> -                   code = 7;
> -                   goto do_fault;
> -               }
> -           } else {
> -               phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
> -           }
> +            if (type == 1) {
> +                if (arm_feature(env, ARM_FEATURE_XSCALE)) {
> +                    phys_addr = (desc & 0xfffff000) | (address & 0xfff);
> +                } else {
> +                    /* Page translation fault.  */
> +                    code = 7;
> +                    goto do_fault;
> +                }
> +            } else {
> +                phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
> +            }
>              ap = (desc >> 4) & 3;
>              *page_size = 0x400;
>              break;
> @@ -5190,18 +5190,18 @@ static int get_phys_addr_mpu(CPUARMState *env,
> uint32_t address,
>
>      *phys_ptr = address;
>      for (n = 7; n >= 0; n--) {
> -       base = env->cp15.c6_region[n];
> -       if ((base & 1) == 0)
> -           continue;
> -       mask = 1 << ((base >> 1) & 0x1f);
> -       /* Keep this shift separate from the above to avoid an
> -          (undefined) << 32.  */
> -       mask = (mask << 1) - 1;
> -       if (((base ^ address) & ~mask) == 0)
> -           break;
> +        base = env->cp15.c6_region[n];
> +        if ((base & 1) == 0)
> +            continue;
> +        mask = 1 << ((base >> 1) & 0x1f);
> +        /* Keep this shift separate from the above to avoid an
> +           (undefined) << 32.  */
> +        mask = (mask << 1) - 1;
> +        if (((base ^ address) & ~mask) == 0)
> +            break;
>      }
>      if (n < 0)
> -       return 2;
> +        return 2;
>
>      if (access_type == 2) {
>          mask = env->cp15.pmsav5_insn_ap;
> @@ -5211,31 +5211,31 @@ static int get_phys_addr_mpu(CPUARMState *env,
> uint32_t address,
>      mask = (mask >> (n * 4)) & 0xf;
>      switch (mask) {
>      case 0:
> -       return 1;
> +        return 1;
>      case 1:
> -       if (is_user)
> -         return 1;
> -       *prot = PAGE_READ | PAGE_WRITE;
> -       break;
> +        if (is_user)
> +          return 1;
> +        *prot = PAGE_READ | PAGE_WRITE;
> +        break;
>      case 2:
> -       *prot = PAGE_READ;
> -       if (!is_user)
> -           *prot |= PAGE_WRITE;
> -       break;
> +        *prot = PAGE_READ;
> +        if (!is_user)
> +            *prot |= PAGE_WRITE;
> +        break;
>      case 3:
> -       *prot = PAGE_READ | PAGE_WRITE;
> -       break;
> +        *prot = PAGE_READ | PAGE_WRITE;
> +        break;
>      case 5:
> -       if (is_user)
> -           return 1;
> -       *prot = PAGE_READ;
> -       break;
> +        if (is_user)
> +            return 1;
> +        *prot = PAGE_READ;
> +        break;
>      case 6:
> -       *prot = PAGE_READ;
> -       break;
> +        *prot = PAGE_READ;
> +        break;
>      default:
> -       /* Bad permission.  */
> -       return 1;
> +        /* Bad permission.  */
> +        return 1;
>      }
>      *prot |= PAGE_EXEC;
>      return 0;
> --
> 1.9.1
>
>
​Reviewed-by: Greg Bellows <greg.bellows@linaro.org>​

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  reply	other threads:[~2015-01-26 22:53 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-01-23 18:20 [Qemu-devel] [PATCH 00/11] target-arm: handle mmu_idx/translation regimes properly Peter Maydell
2015-01-23 18:20 ` [Qemu-devel] [PATCH 01/11] cpu_ldst.h: Allow NB_MMU_MODES to be 7 Peter Maydell
2015-01-23 20:16   ` Greg Bellows
2015-01-24  1:05     ` Peter Maydell
2015-01-23 20:33   ` Paolo Bonzini
2015-01-23 18:20 ` [Qemu-devel] [PATCH 02/11] target-arm: Make arm_current_el() return sensible values for M profile Peter Maydell
2015-01-23 21:38   ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 03/11] target-arm/translate-a64: Fix wrong mmu_idx usage for LDT/STT Peter Maydell
2015-01-23 20:58   ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 04/11] target-arm: Define correct mmu_idx values and pass them in TB flags Peter Maydell
2015-01-23 21:44   ` Greg Bellows
2015-01-24  1:12     ` Peter Maydell
2015-01-24 16:36       ` Greg Bellows
2015-01-24 19:31         ` Peter Maydell
2015-01-26 11:29           ` Peter Maydell
2015-01-27 19:30   ` Peter Maydell
2015-01-28 21:57   ` Greg Bellows
2015-01-28 22:34     ` Peter Maydell
2015-01-29 15:20       ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 05/11] target-arm: Use correct mmu_idx for unprivileged loads and stores Peter Maydell
2015-01-26 14:40   ` Greg Bellows
2015-01-26 14:56     ` Peter Maydell
2015-01-26 19:34       ` Greg Bellows
2015-01-26 20:37         ` Peter Maydell
2015-01-26 22:01           ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 06/11] target-arm: Don't define any MMU_MODE*_SUFFIXes Peter Maydell
2015-01-26 20:16   ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 07/11] target-arm: Split AArch64 cases out of ats_write() Peter Maydell
2015-01-26 20:30   ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 08/11] target-arm: Pass mmu_idx to get_phys_addr() Peter Maydell
2015-01-26 21:41   ` Greg Bellows
2015-01-26 21:55     ` Peter Maydell
2015-01-23 18:20 ` [Qemu-devel] [PATCH 09/11] target-arm: Use mmu_idx in get_phys_addr() Peter Maydell
2015-01-27 17:57   ` Greg Bellows
2015-01-27 18:12     ` Peter Maydell
2015-01-27 19:49       ` Greg Bellows
2015-01-27 19:59         ` Peter Maydell
2015-01-28 21:37   ` Greg Bellows
2015-01-28 22:30     ` Peter Maydell
2015-01-29 15:19       ` Greg Bellows
2015-01-23 18:20 ` [Qemu-devel] [PATCH 10/11] target-arm: Reindent ancient page-table-walk code Peter Maydell
2015-01-26 22:53   ` Greg Bellows [this message]
2015-01-23 18:20 ` [Qemu-devel] [PATCH 11/11] target-arm: Fix brace style in reindented code Peter Maydell
2015-01-26 22:56   ` Greg Bellows

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