From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:48824)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YFpQF-0008Do-2u
	for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:34:08 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YFpQB-0003hw-Np
	for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:34:06 -0500
Received: from mail-qc0-f176.google.com ([209.85.216.176]:38129)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <greg.bellows@linaro.org>) id 1YFpQB-0003ho-J4
	for qemu-devel@nongnu.org; Mon, 26 Jan 2015 14:34:03 -0500
Received: by mail-qc0-f176.google.com with SMTP id c9so8673360qcz.7
	for <qemu-devel@nongnu.org>; Mon, 26 Jan 2015 11:34:03 -0800 (PST)
MIME-Version: 1.0
In-Reply-To: <CAFEAcA9fpdz=B2Xe0ynapOoQDXd7oV4ZiVC4kYTxnDEfhpr_Dg@mail.gmail.com>
References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org>
	<1422037228-5363-6-git-send-email-peter.maydell@linaro.org>
	<CAOgzsHUsWqT38ygogVooMPk4HNEFA290F3-QAo41AxYdM1LhJg@mail.gmail.com>
	<CAFEAcA9fpdz=B2Xe0ynapOoQDXd7oV4ZiVC4kYTxnDEfhpr_Dg@mail.gmail.com>
Date: Mon, 26 Jan 2015 13:34:02 -0600
Message-ID: <CAOgzsHU_woa-KUcjic0V98CQKKBt1pbU6Gjcw10a8hf2JaHaPw@mail.gmail.com>
From: Greg Bellows <greg.bellows@linaro.org>
Content-Type: multipart/alternative; boundary=001a113a9764840b51050d9338f2
Subject: Re: [Qemu-devel] [PATCH 05/11] target-arm: Use correct mmu_idx for
 unprivileged loads and stores
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Andrew Jones <drjones@redhat.com>, =?UTF-8?B?QWxleCBCZW5uw6ll?= <alex.bennee@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>, Patch Tracking <patches@linaro.org>

--001a113a9764840b51050d9338f2
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

On Mon, Jan 26, 2015 at 8:56 AM, Peter Maydell <peter.maydell@linaro.org>
wrote:

> On 26 January 2015 at 14:40, Greg Bellows <greg.bellows@linaro.org> wrote=
:
> > On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell <
> peter.maydell@linaro.org>
> > wrote:
> >>
> >> The MMU index to use for unprivileged loads and stores is more
> >> complicated than we currently implement:
> >>  * for A64, it should be "if at EL1, access as if EL0; otherwise
> >>    access at current EL"
> >>  * for A32/T32, it should be "if EL2, UNPREDICTABLE; otherwise
> >>    access as if at EL0".
> >>
> >
> > The wording between the specs appears to be almost identical, curious w=
hy
> > the handling is different?
>
> Because that's what the ARM ARM specifies. Compare C3.2.5 (A64 LDT &c)
> with F7.1.95 (A32/T32 LDRT).
>
=E2=80=8B=E2=80=8B

=E2=80=8BI had been comparing the wording of ARMv8 - F1.6.3 and =E2=80=8BAR=
Mv7 - A4.6.3.
After comparing the LDRT instructions between A64 (C6.6.97) and A32
(F7.1.95), I am still missing the distinction that warrants the following
different behavior:

- EL2 is unpredictable in both A64 and A32, but in one case we treat it as
such and the other we demote it to NS/EL0 to allow it.
- EL3 is demoted to S/EL0 in one case but remains EL3 in the other.


>
> -- PMM
>

--001a113a9764840b51050d9338f2
Content-Type: text/html; charset=UTF-8
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr"><div class=3D"gmail_default" style=3D"font-family:arial,he=
lvetica,sans-serif"><br></div><div class=3D"gmail_extra"><br><div class=3D"=
gmail_quote">On Mon, Jan 26, 2015 at 8:56 AM, Peter Maydell <span dir=3D"lt=
r">&lt;<a href=3D"mailto:peter.maydell@linaro.org" target=3D"_blank">peter.=
maydell@linaro.org</a>&gt;</span> wrote:<br><blockquote class=3D"gmail_quot=
e" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">=
<span>On 26 January 2015 at 14:40, Greg Bellows &lt;<a href=3D"mailto:greg.=
bellows@linaro.org" target=3D"_blank">greg.bellows@linaro.org</a>&gt; wrote=
:<br>
&gt; On Fri, Jan 23, 2015 at 12:20 PM, Peter Maydell &lt;<a href=3D"mailto:=
peter.maydell@linaro.org" target=3D"_blank">peter.maydell@linaro.org</a>&gt=
;<br>
&gt; wrote:<br>
&gt;&gt;<br>
&gt;&gt; The MMU index to use for unprivileged loads and stores is more<br>
&gt;&gt; complicated than we currently implement:<br>
&gt;&gt;=C2=A0 * for A64, it should be &quot;if at EL1, access as if EL0; o=
therwise<br>
&gt;&gt;=C2=A0 =C2=A0 access at current EL&quot;<br>
&gt;&gt;=C2=A0 * for A32/T32, it should be &quot;if EL2, UNPREDICTABLE; oth=
erwise<br>
&gt;&gt;=C2=A0 =C2=A0 access as if at EL0&quot;.<br>
&gt;&gt;<br>
&gt;<br>
&gt; The wording between the specs appears to be almost identical, curious =
why<br>
&gt; the handling is different?<br>
<br>
</span>Because that&#39;s what the ARM ARM specifies. Compare C3.2.5 (A64 L=
DT &amp;c)<br>
with F7.1.95 (A32/T32 LDRT).<br></blockquote><div><div class=3D"gmail_defau=
lt" style=3D"font-family:arial,helvetica,sans-serif">=E2=80=8B=E2=80=8B</di=
v><br></div><div><div class=3D"gmail_default" style=3D"font-family:arial,he=
lvetica,sans-serif">=E2=80=8BI had been comparing the wording of ARMv8 - F1=
.6.3 and =E2=80=8BARMv7 - A4.6.3.=C2=A0</div><div class=3D"gmail_default" s=
tyle=3D"font-family:arial,helvetica,sans-serif">After comparing the LDRT in=
structions between A64 (C6.6.97) and A32 (F7.1.95), I am still missing the =
distinction that warrants the following different behavior:</div><div class=
=3D"gmail_default" style=3D"font-family:arial,helvetica,sans-serif"><br></d=
iv><div class=3D"gmail_default" style=3D"font-family:arial,helvetica,sans-s=
erif">- EL2 is unpredictable in both A64 and A32, but in one case we treat =
it as such and the other we demote it to NS/EL0 to allow it.</div><div clas=
s=3D"gmail_default" style=3D"font-family:arial,helvetica,sans-serif">- EL3 =
is demoted to S/EL0 in one case but remains EL3 in the other.</div></div><d=
iv>=C2=A0</div><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex=
;border-left:1px #ccc solid;padding-left:1ex">
<br>
-- PMM<br>
</blockquote></div><br></div></div>

--001a113a9764840b51050d9338f2--