From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGqtG-0005AK-BQ for qemu-devel@nongnu.org; Thu, 29 Jan 2015 10:20:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YGqtD-0004dE-Io for qemu-devel@nongnu.org; Thu, 29 Jan 2015 10:20:18 -0500 Received: from mail-qg0-f50.google.com ([209.85.192.50]:42533) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YGqtD-0004d1-By for qemu-devel@nongnu.org; Thu, 29 Jan 2015 10:20:15 -0500 Received: by mail-qg0-f50.google.com with SMTP id f51so29436557qge.9 for ; Thu, 29 Jan 2015 07:20:15 -0800 (PST) MIME-Version: 1.0 In-Reply-To: References: <1422037228-5363-1-git-send-email-peter.maydell@linaro.org> <1422037228-5363-5-git-send-email-peter.maydell@linaro.org> Date: Thu, 29 Jan 2015 09:20:14 -0600 Message-ID: From: Greg Bellows Content-Type: multipart/alternative; boundary=001a11c2b31c5ed7d6050dcc06c1 Subject: Re: [Qemu-devel] [PATCH 04/11] target-arm: Define correct mmu_idx values and pass them in TB flags List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: "Edgar E. Iglesias" , Andrew Jones , =?UTF-8?B?QWxleCBCZW5uw6ll?= , QEMU Developers , Patch Tracking --001a11c2b31c5ed7d6050dcc06c1 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On Wed, Jan 28, 2015 at 4:34 PM, Peter Maydell wrote: > On 28 January 2015 at 21:57, Greg Bellows wrote= : > > After getting through patch 9, I wonder if the TB NS bit can also be > removed > > as it is implied in the MMU index. > > No, because for a 32-bit EL3 we are always running under a Secure > translation regime (S1E3) but the TBFLAG_NS bit may be either 0 or > 1 depending on the value of the SCR.NS bit. > > =E2=80=8BThat is correct.=E2=80=8B > -- PMM > --001a11c2b31c5ed7d6050dcc06c1 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable


On Wed, Jan 28, 2015 at 4:34 PM, Peter Maydell <peter.= maydell@linaro.org> wrote:
= On 28 January 2015 at 21:57, Greg Bellows <greg.bellows@linaro.org> wrote:
> After getting through patch 9, I wonder if the TB NS bit can also be r= emoved
> as it is implied in the MMU index.

No, because for a 32-bit EL3 we are always running under a Secure translation regime (S1E3) but the TBFLAG_NS bit may be either 0 or
1 depending on the value of the SCR.NS bit.


=E2=80=8BThat is correct.=E2=80=8B<= /div>
=C2=A0
-- PMM

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