From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4B25C4338F for ; Wed, 4 Aug 2021 14:39:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9F10060F01 for ; Wed, 4 Aug 2021 14:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238043AbhHDOkL (ORCPT ); Wed, 4 Aug 2021 10:40:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237935AbhHDOkE (ORCPT ); Wed, 4 Aug 2021 10:40:04 -0400 Received: from mail-vk1-xa2e.google.com (mail-vk1-xa2e.google.com [IPv6:2607:f8b0:4864:20::a2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01D32C061798 for ; Wed, 4 Aug 2021 07:39:51 -0700 (PDT) Received: by mail-vk1-xa2e.google.com with SMTP id o2so493456vkb.4 for ; Wed, 04 Aug 2021 07:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=rDKZtg82NP3ddCZ+CbKtTQlVqMfRo/3JfYFc/Sav3bE=; b=Rb4w2JW9NDUtFI5B1DdY4p2VknlohGp3Ak2rkEyHilaSfQWGfO0PvM1LI8VTGSK58E E5E1B7V9pL3lsFa9AlJN5av9Qj+fCiZP+6tceSKxdI88Ba47f90C3X8Z4yv2iUc+dHm0 I4ldJ6XAhqprsW6XOH5F45fxk02OUBmUTwEKyL9gV6aedQ/k3CI1uHi8cB5PtGBQKZG6 Odz6nToeGDrD5vdlizhxdCzailrpXe2J3KfMjoivaI8rPBD1almFcOU+6j2dUPFr0uer zfNkuOoXistHWz3jiy1hDLDplsrrln/1yOHA4dOaP9Z9uNs+SeRuriIj+AuA6y67mGyN xNTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rDKZtg82NP3ddCZ+CbKtTQlVqMfRo/3JfYFc/Sav3bE=; b=sP8t+raQx32lpl9U9jtuy9gEVRQPXZqqz2aj6/Bel3fnsNrH+zbntREWc9BAMCPbOc jifb05ve4b0ZMXoa+hqZ7LQ6wY1t4DXiJ+jVk33LJv4wc92oOs97xwKFU/uqduYZL9mC ii+EBJZSR/k5Edi3/CBcn77lesr2OMEtgyxjeNxsQBrZcOr0sry9knaCt4S5sFyMzQya zw8+pLH8Y2Z4JANzUfrkc59ysOuAtJYyaXcnzdDNp0lcVODkTJmkZBUpa/fLRbXVvxP8 Dny/ninU9DU9k3x3innGAkr/V9qUrEsTeEPbfP1jiaO6Oes9Uvpt1vQt2zHL2y1pLi0b IEXQ== X-Gm-Message-State: AOAM533KejTlcPbJnspn9ZNlws65iLjhJir2b5a71iacG+Xw+Oy/5+4A 1T+Pp3fcaERTYx621M9RNGjRxQZ76uYpXUbFCboHiw== X-Google-Smtp-Source: ABdhPJxlsfrubol74U2vzDZDlR75ZOAD7I215GfcgIYKIkBbyLzJAazUw8L/PPcVieLCSBWNf4qgTYF7TKl9M+mp1Eo= X-Received: by 2002:a05:6122:549:: with SMTP id y9mr5395608vko.7.1628087990034; Wed, 04 Aug 2021 07:39:50 -0700 (PDT) MIME-Version: 1.0 References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> In-Reply-To: <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> From: Sam Protsenko Date: Wed, 4 Aug 2021 17:39:38 +0300 Message-ID: Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support To: Marc Zyngier Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi Marc, On Fri, 30 Jul 2021 at 19:50, Marc Zyngier wrote: > > On 2021-07-30 15:49, Sam Protsenko wrote: > > Samsung Exynos850 is ARMv8-based mobile-oriented SoC. > > > > Features: > > * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz > > * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s) > > * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit > > * Modem: 4G LTE, 3G, GSM/GPRS/EDGE > > * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0 > > * GPU: Mali-G52 MP1 > > * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec > > * Display: Full HD+ (2520x1080)@60fps LCD > > * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC > > * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC, > > Audio > > > > This patch adds minimal SoC support. Particular board device tree files > > can include exynos850.dtsi file to get SoC related nodes, and then > > reference those nodes further as needed. > > > > Signed-off-by: Sam Protsenko > > --- > > .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++ > > arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 + > > arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++ > > 3 files changed, 1057 insertions(+) > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi > > > > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > new file mode 100644 > > index 000000000000..4cf0a22cc6db > > [...] > > > + gic: interrupt-controller@12a00000 { > > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > > One thing for sure, it cannot be both. And given that it is > an A55-based SoC, it isn't either. It is more likely a GIC400. > Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2. > > + #interrupt-cells = <3>; > > + #address-cells = <0>; > > + interrupt-controller; > > + reg = <0x0 0x12a01000 0x1000>, > > + <0x0 0x12a02000 0x1000>, > > This is wrong. It is architecturally set to 8kB. > Nice catch! Actually there is an error (typo?) in SoC's TRM, saying that Virtual Interface Control Register starts at 0x3000 offset (from 0x12a00000), where it obviously should be 0x4000, that's probably where this dts error originates from. Btw, I'm also seeing the same error in exynos7.dtsi. Though I don't have a TRM for Exynos7 SoCs, so not sure if I should go ahead and fix that too. Anyway, for Exynos850, I'll fix that in v2 series. > > + <0x0 0x12a04000 0x2000>, > > + <0x0 0x12a06000 0x2000>; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > 4? With 8 CPUs? > Will be fixed in v2, thanks. > I also find it curious that you went through the unusual > (and IMO confusing) effort to allocate a name to each and > every SPI in the system, but didn't do it for any on the PPIs... > Yeah, after some consideration I removed the whole interrupts header and used hard-coded values instead. I probably felt it would be right thing to have, just because there is no public TRM for Exynos850, thus documenting interrupts somewhere would be nice. But that reasoning is wrong, as trying to mix that kind of documentation with code just clutters it. The right thing to do is probably just provide a public TRM, but that's not for me to decide, alas :) Anyway, will be fixed in v2. > > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <26000000>; > > No, please. Fix the firmware to program CNTFRQ_EL0 on each > and every CPU. This isn't 2012 anymore. > Ok, will remove that property in v2. Though it looks like CNTFRQ_EL0 register can be only changed in EL3 execution level, so I'll have to ask the vendor to fix their BL31 or whatever. But that might take some time, so I'll have to keep "clock-frequency" workaround in my local tree for now, to make scheduler work. > You are also missing the hypervisor virtual timer interrupt. > Checked SoC TRM, there is no PPI for hypervisor virtual timer interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 ARM and TRM, almost no description of it. Also, I checked other platforms, and seems like everyone does the same (having only 4 interrupts). And I wasn't able to find any documentation on that, so I guess I'll leave it as is, if you don't mind. > > + use-clocksource-only; > > + use-physical-timer; > > Thankfully, these two properties do not exist. > Yeah, that's just some leftover from vendor's kernel, overlook by me... Will remove in v2, thanks. > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A0AEC4338F for ; Wed, 4 Aug 2021 14:41:30 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5D84660F01 for ; Wed, 4 Aug 2021 14:41:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5D84660F01 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=P/EG7zpbyJYTo9PGyrfdSJxyg42CKS7IyuG9rayDxdQ=; b=LHFhmT4IG1TgWN SxR+E+z2HWkzzgzYibtqAn0vfs6xpPjaE/mCDLp/7peuOldKv3XSoYePu3QEfMv8qWcrs2ct+AYis 2smwTag4bQtUfISqP4MDFaiZBKV7SmUQ5mPxVqJ4zRJYLfa3wQfvVCZWYRJdWvwpZiaJJ1WnyZZIX b6CEKFVgWL6yQcpO1p0m9i/UfVLu4UFsBIaL0e18lKHAex8AeDN98kFfyI6/Ri7JLl4OiNvYG8mwT vObgIhiIk52bOaFJYmUwXluwfAf+BaMXss1JeFrrkm+byN8UDCZzjga4KKLhlELJbmyIG4ZRgq0mM gEz4yamKSPIOs6CXxT8w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mBI3o-006TWr-QG; Wed, 04 Aug 2021 14:39:57 +0000 Received: from mail-vk1-xa2d.google.com ([2607:f8b0:4864:20::a2d]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mBI3k-006TV7-J6 for linux-arm-kernel@lists.infradead.org; Wed, 04 Aug 2021 14:39:54 +0000 Received: by mail-vk1-xa2d.google.com with SMTP id p6so494690vkg.6 for ; Wed, 04 Aug 2021 07:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=rDKZtg82NP3ddCZ+CbKtTQlVqMfRo/3JfYFc/Sav3bE=; b=Rb4w2JW9NDUtFI5B1DdY4p2VknlohGp3Ak2rkEyHilaSfQWGfO0PvM1LI8VTGSK58E E5E1B7V9pL3lsFa9AlJN5av9Qj+fCiZP+6tceSKxdI88Ba47f90C3X8Z4yv2iUc+dHm0 I4ldJ6XAhqprsW6XOH5F45fxk02OUBmUTwEKyL9gV6aedQ/k3CI1uHi8cB5PtGBQKZG6 Odz6nToeGDrD5vdlizhxdCzailrpXe2J3KfMjoivaI8rPBD1almFcOU+6j2dUPFr0uer zfNkuOoXistHWz3jiy1hDLDplsrrln/1yOHA4dOaP9Z9uNs+SeRuriIj+AuA6y67mGyN xNTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=rDKZtg82NP3ddCZ+CbKtTQlVqMfRo/3JfYFc/Sav3bE=; b=by7TQU9F16BlhnpLYfhJchizmFC/G+Iu8Pop8ipN53HixKlkZ6abcNfz/zSgRvIoA4 Cuncx7ZuinmEoYtpO6xBzYbLSb5P+s14/GSe7k+Evc/tzssoBgklZSvUvpi7PVwaPJxc N0SHjBHB7XSCe9wHdd637umTYlt+pAvCFflYDAetq0CpAT9d7/XKP+Q8+oQKKxx2Mztt 2VNcEj4fbWw3C43UCuNsHIlFAXaoZS8yGfMEY9nDKXKjiqBoVeIGZaQHlF7LBAOcpOVt cbacwH/zKY0w/C20o4fyS/tQjOGZDIzTkPzlaz5g2u1QQPYySothq8loG+p1FfZsa3vZ pH2g== X-Gm-Message-State: AOAM532QXpKjGnCR3Jw03QWoAgYlfAa6Hwbmu/+C/popme+x69rjTMZg m0MfUjl+iXxxcSPF/56+XcmVYnGBXAtuwWD5hw2Ndg== X-Google-Smtp-Source: ABdhPJxlsfrubol74U2vzDZDlR75ZOAD7I215GfcgIYKIkBbyLzJAazUw8L/PPcVieLCSBWNf4qgTYF7TKl9M+mp1Eo= X-Received: by 2002:a05:6122:549:: with SMTP id y9mr5395608vko.7.1628087990034; Wed, 04 Aug 2021 07:39:50 -0700 (PDT) MIME-Version: 1.0 References: <20210730144922.29111-1-semen.protsenko@linaro.org> <20210730144922.29111-13-semen.protsenko@linaro.org> <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> In-Reply-To: <15871f8ced3c757fad1ab3b6e62c4e64@misterjones.org> From: Sam Protsenko Date: Wed, 4 Aug 2021 17:39:38 +0300 Message-ID: Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support To: Marc Zyngier Cc: Sylwester Nawrocki , Chanwoo Choi , Krzysztof Kozlowski , Linus Walleij , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette , Jiri Slaby , Greg Kroah-Hartman , Charles Keepax , Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree , linux-arm Mailing List , linux-clk , "open list:GPIO SUBSYSTEM" , Linux Kernel Mailing List , Linux Samsung SOC , "open list:SERIAL DRIVERS" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210804_073952_696589_54471094 X-CRM114-Status: GOOD ( 39.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Fri, 30 Jul 2021 at 19:50, Marc Zyngier wrote: > > On 2021-07-30 15:49, Sam Protsenko wrote: > > Samsung Exynos850 is ARMv8-based mobile-oriented SoC. > > > > Features: > > * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz > > * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s) > > * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit > > * Modem: 4G LTE, 3G, GSM/GPRS/EDGE > > * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0 > > * GPU: Mali-G52 MP1 > > * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec > > * Display: Full HD+ (2520x1080)@60fps LCD > > * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC > > * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC, > > Audio > > > > This patch adds minimal SoC support. Particular board device tree files > > can include exynos850.dtsi file to get SoC related nodes, and then > > reference those nodes further as needed. > > > > Signed-off-by: Sam Protsenko > > --- > > .../boot/dts/exynos/exynos850-pinctrl.dtsi | 782 ++++++++++++++++++ > > arch/arm64/boot/dts/exynos/exynos850-usi.dtsi | 30 + > > arch/arm64/boot/dts/exynos/exynos850.dtsi | 245 ++++++ > > 3 files changed, 1057 insertions(+) > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi > > create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi > > > > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi > > new file mode 100644 > > index 000000000000..4cf0a22cc6db > > [...] > > > + gic: interrupt-controller@12a00000 { > > + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; > > One thing for sure, it cannot be both. And given that it is > an A55-based SoC, it isn't either. It is more likely a GIC400. > Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2. > > + #interrupt-cells = <3>; > > + #address-cells = <0>; > > + interrupt-controller; > > + reg = <0x0 0x12a01000 0x1000>, > > + <0x0 0x12a02000 0x1000>, > > This is wrong. It is architecturally set to 8kB. > Nice catch! Actually there is an error (typo?) in SoC's TRM, saying that Virtual Interface Control Register starts at 0x3000 offset (from 0x12a00000), where it obviously should be 0x4000, that's probably where this dts error originates from. Btw, I'm also seeing the same error in exynos7.dtsi. Though I don't have a TRM for Exynos7 SoCs, so not sure if I should go ahead and fix that too. Anyway, for Exynos850, I'll fix that in v2 series. > > + <0x0 0x12a04000 0x2000>, > > + <0x0 0x12a06000 0x2000>; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > 4? With 8 CPUs? > Will be fixed in v2, thanks. > I also find it curious that you went through the unusual > (and IMO confusing) effort to allocate a name to each and > every SPI in the system, but didn't do it for any on the PPIs... > Yeah, after some consideration I removed the whole interrupts header and used hard-coded values instead. I probably felt it would be right thing to have, just because there is no public TRM for Exynos850, thus documenting interrupts somewhere would be nice. But that reasoning is wrong, as trying to mix that kind of documentation with code just clutters it. The right thing to do is probably just provide a public TRM, but that's not for me to decide, alas :) Anyway, will be fixed in v2. > > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > > + > + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > > + clock-frequency = <26000000>; > > No, please. Fix the firmware to program CNTFRQ_EL0 on each > and every CPU. This isn't 2012 anymore. > Ok, will remove that property in v2. Though it looks like CNTFRQ_EL0 register can be only changed in EL3 execution level, so I'll have to ask the vendor to fix their BL31 or whatever. But that might take some time, so I'll have to keep "clock-frequency" workaround in my local tree for now, to make scheduler work. > You are also missing the hypervisor virtual timer interrupt. > Checked SoC TRM, there is no PPI for hypervisor virtual timer interrupt, and no mentioning of it at all. Likewise, I checked ARMv8 ARM and TRM, almost no description of it. Also, I checked other platforms, and seems like everyone does the same (having only 4 interrupts). And I wasn't able to find any documentation on that, so I guess I'll leave it as is, if you don't mind. > > + use-clocksource-only; > > + use-physical-timer; > > Thankfully, these two properties do not exist. > Yeah, that's just some leftover from vendor's kernel, overlook by me... Will remove in v2, thanks. > Thanks, > > M. > -- > Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel