From mboxrd@z Thu Jan  1 00:00:00 1970
From: Simon Glass <sjg@chromium.org>
Date: Thu, 21 Nov 2019 06:50:20 -0700
Subject: [U-Boot] [PATCH v3 086/108] spi: ich: Add TPL support
In-Reply-To: <CAEUhbmWi8SY5tg6G4YSvuEiu4AJ7=4GyZHpfbcqnd7eJ1V=hog@mail.gmail.com>
References: <20191021033913.220758-22-sjg@chromium.org>
 <20191021033913.220758-81-sjg@chromium.org>
 <CAEUhbmWi8SY5tg6G4YSvuEiu4AJ7=4GyZHpfbcqnd7eJ1V=hog@mail.gmail.com>
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Hi Bin,

On Tue, 19 Nov 2019 at 07:52, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Simon,
>
> On Mon, Oct 21, 2019 at 11:40 AM Simon Glass <sjg@chromium.org> wrote:
> >
> > In TPL we want to reduce code size and support running with CONFIG_PCI
> > disabled. Add special code to handle this using a fixed BAR programmed
> > into the SPI on boot. Also cache the SPI flash to speed up boot.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v3: None
> > Changes in v2: None
> >
> >  drivers/spi/ich.c | 46 ++++++++++++++++++++++++++++++++++++++++++----
> >  1 file changed, 42 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
> > index ec0f77f6e40..daa69c25a3a 100644
> > --- a/drivers/spi/ich.c
> > +++ b/drivers/spi/ich.c
> > @@ -19,8 +19,10 @@
> >  #include <spi.h>
> >  #include <spi_flash.h>
> >  #include <spi-mem.h>
> > +#include <spl.h>
> >  #include <asm/fast_spi.h>
> >  #include <asm/io.h>
> > +#include <asm/mtrr.h>
> >
> >  #include "ich.h"
> >
> > @@ -114,6 +116,8 @@ static bool ich9_can_do_33mhz(struct udevice *dev)
> >  {
> >         u32 fdod, speed;
> >
> > +       if (!CONFIG_IS_ENABLED(PCI))
> > +               return false;
> >         /* Observe SPI Descriptor Component Section 0 */
> >         dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
> >
> > @@ -705,6 +709,15 @@ static int ich_init_controller(struct udevice *dev,
> >                                struct ich_spi_platdata *plat,
> >                                struct ich_spi_priv *ctlr)
> >  {
> > +       if (spl_phase() == PHASE_TPL) {
> > +               struct ich_spi_platdata *plat = dev_get_platdata(dev);
> > +               int ret;
> > +
> > +               ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
>
> Can we move the fast_spi_early_init() contents to ich_spi_probe(),
> where the bios_cntl register is programmed to disable the write
> protect for ICH_V7? This helps reading as it's disabling write
> protect, but for different ICH SPI variants.

That driver is not included in TPL. It adds about 7KB to code size and
puts us very close to the limit.

Regards,
Simon