Hi,

> This patch adds support for the APM X-Gene SoC memory controller EDAC driver
> for DT.
>
> v8:
> * Change ASM_EDAC_H to __ASM_EDAC_H in file edac.h
> * Add WARN_ONCE in stub function atomic_scrub
> * Update DTS binding documentation (with only memory controller node)
> * Temporary remove L1/L2, L3, and SoC driver code and update memory driver
> code accordingly

What does that mean exactly? They'll get added later?

It is not include in this first patch set. Yes, it will be added later. I will response along with Arnd subsequent email.

It is called now xgene_edac_mc.c. Am I to expect more
xgene_edac_<functional_unit>.c submissions?

Yes

What happened to building
everything around the shared IRQ handler?

It was discussed with Rob already in previous email. As we don't touch the shared status registers besides reading status, it will just register as shared interrupt.

Also, I see this SOB chain in some of the patches:

Signed-off-by: Feng Kan <fkan@apm.com>
Signed-off-by: Loc Ho <lho@apm.com>

and it is not clear who did what, from looking at the chain.

If you both authored the patches, you can write

Originally-by: Feng
[ Loc: did this and that]
Signed-off-by: Loc

for example.

See Documentation/SubmittingPatches for more info.

Okay... Feng was the originally author.

-Loc