From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23082C432C0 for ; Tue, 3 Dec 2019 15:44:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E673D2070A for ; Tue, 3 Dec 2019 15:44:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=arista.com header.i=@arista.com header.b="EBwqc6Mu" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727069AbfLCPoU (ORCPT ); Tue, 3 Dec 2019 10:44:20 -0500 Received: from mail-pj1-f65.google.com ([209.85.216.65]:39941 "EHLO mail-pj1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726086AbfLCPoT (ORCPT ); Tue, 3 Dec 2019 10:44:19 -0500 Received: by mail-pj1-f65.google.com with SMTP id s35so1672154pjb.7 for ; Tue, 03 Dec 2019 07:44:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arista.com; s=googlenew; h=mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=9ZkhQrbE0pqWo4Xrfbt5no2EyvavM8680V6oMcMbppE=; b=EBwqc6MulSxDWmm7FdPAlxIr1bsXOSVCfKzrNL1doUXKxjR7GgAOrbgPO8OBy0Z3G9 Bm5CZmA9BZ/TbmkovBpvwhZIJ30cFgj4XLfb9ILKVsr87CAknH81elcvsIszKP1NoAKR aGoWTjt56RQiNo6Q7npeqkPdw3vqrupsnmyNtB545Okihe9VojG2/NA2Ckyu3YYNO8Ta C1ZIdxjKY/1vUndUI8IXOAd6NhogSj/gSUsdveQKA62ryk1FVsjhdXZ10hz3jkr3p0Dh n+eWdL0KL9P0/2mppivVB0C8itzjIFmTufIqXQ7MSmQ672wzoes8agSVU8kh0p/b22CV uykQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:subject:from:in-reply-to:date:cc :content-transfer-encoding:message-id:references:to; bh=9ZkhQrbE0pqWo4Xrfbt5no2EyvavM8680V6oMcMbppE=; b=UVc/qj/TSKcujkKg7uPp0eyjVtH+iaWj+q6z7SFvdGR/lH+EBVznx7q9BgYGoQbgRN b/x3NgORPyOSiUwm0abc/0rjt1Z2KEv3MlAiPRkzOW5UtBCY5rkJp5pnEyqCtiy6TeQz tJpM+lFYj3NDXiMan2qWBkTWB4grwGu9PwBGjwrNTuvK+qaCkWmfIqYMtdfVpRQqTeJl eOsSae4aAcrlRRyo//JOU7FyjmGG+pHkufvJ23tGvJkr/Q3yBUywmXUYByA5VrDwqEOS yuiXG3jUeXQJt+H+wvQMo9cDS7PYQaqbBfs14x89uB70d9NB9cxqtNt6Y4q0R08vGstO YXLA== X-Gm-Message-State: APjAAAUwEcyjJ14tTav8H+ejWj9uPrqe0SmflONoqxGi7ohufptKfW+q RsgWUUAemnLNV2nNxCzab8fu4Q== X-Google-Smtp-Source: APXvYqwi1quFBuB5qYP3TcIJe8VNkDjJWejd8MLtlpQR7IQidLMT9GSnDbiV/IMnm1WNzKlpfKtONQ== X-Received: by 2002:a17:90a:d353:: with SMTP id i19mr6306671pjx.43.1575387858722; Tue, 03 Dec 2019 07:44:18 -0800 (PST) Received: from [10.83.42.232] ([217.173.96.166]) by smtp.gmail.com with ESMTPSA id e11sm3953969pgh.54.2019.12.03.07.44.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Dec 2019 07:44:17 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 12.2 \(3445.102.3\)) Subject: [PATCH v6 3/3] PCI: Add DMA alias quirk for PLX PEX NTB From: James Sewart In-Reply-To: Date: Tue, 3 Dec 2019 15:44:15 +0000 Cc: Logan Gunthorpe , Christoph Hellwig , Dmitry Safonov <0x7f454c46@gmail.com>, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Dmitry Safonov , Alex Williamson , Bjorn Helgaas Content-Transfer-Encoding: quoted-printable Message-Id: References: <910070E3-7964-4549-B77F-EC7FC6144503@arista.com> To: linux-pci@vger.kernel.org X-Mailer: Apple Mail (2.3445.102.3) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PLX PEX NTB forwards DMA transactions using Requester ID's that don't exist as PCI devices. The devfn for a transaction is used as an index into a lookup table storing the origin of a transaction on the other side of the bridge. This patch aliases all possible devfn's to the NTB device so that any transaction coming in is governed by the mappings for the NTB. Reviewed-by: Logan Gunthorpe Signed-off-by: James Sewart --- drivers/pci/quirks.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0f3f5afc73fd..3a67049ca630 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5315,6 +5315,21 @@ SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ =20 +/* + * PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. = These IDs + * are used to forward responses to the originator on the other side of = the + * NTB. Alias all possible IDs to the NTB to permit access when the = IOMMU is + * turned on. + */ +static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) +{ + pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); + /* PLX NTB may use all 256 devfns */ + pci_add_dma_alias(pdev, 0, 256); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, = quirk_plx_ntb_dma_alias); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, = quirk_plx_ntb_dma_alias); + /* * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS = does * not always reset the secondary Nvidia GPU between reboots if the = system --=20 2.24.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7328C432C3 for ; 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Tue, 03 Dec 2019 07:44:18 -0800 (PST) Received: from [10.83.42.232] ([217.173.96.166]) by smtp.gmail.com with ESMTPSA id e11sm3953969pgh.54.2019.12.03.07.44.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 03 Dec 2019 07:44:17 -0800 (PST) Mime-Version: 1.0 (Mac OS X Mail 12.2 \(3445.102.3\)) Subject: [PATCH v6 3/3] PCI: Add DMA alias quirk for PLX PEX NTB In-Reply-To: Date: Tue, 3 Dec 2019 15:44:15 +0000 Message-Id: References: <910070E3-7964-4549-B77F-EC7FC6144503@arista.com> To: linux-pci@vger.kernel.org X-Mailer: Apple Mail (2.3445.102.3) Cc: Alex Williamson , Dmitry Safonov , Dmitry Safonov <0x7f454c46@gmail.com>, linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, Bjorn Helgaas , Logan Gunthorpe X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: James Sewart via iommu Reply-To: James Sewart Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" The PLX PEX NTB forwards DMA transactions using Requester ID's that don't exist as PCI devices. The devfn for a transaction is used as an index into a lookup table storing the origin of a transaction on the other side of the bridge. This patch aliases all possible devfn's to the NTB device so that any transaction coming in is governed by the mappings for the NTB. Reviewed-by: Logan Gunthorpe Signed-off-by: James Sewart --- drivers/pci/quirks.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 0f3f5afc73fd..3a67049ca630 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5315,6 +5315,21 @@ SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ +/* + * PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. These IDs + * are used to forward responses to the originator on the other side of the + * NTB. Alias all possible IDs to the NTB to permit access when the IOMMU is + * turned on. + */ +static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) +{ + pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); + /* PLX NTB may use all 256 devfns */ + pci_add_dma_alias(pdev, 0, 256); +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); + /* * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does * not always reset the secondary Nvidia GPU between reboots if the system -- 2.24.0 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu