RE: [PATCH 1/7] dt-bindings: clk: r9a07g044-cpg: Update clock definitions

[Biju Das <biju.das.jz@bp.renesas.com>]

Hi Geert,

Thanks for the feedback.

> Subject: Re: [PATCH 1/7] dt-bindings: clk: r9a07g044-cpg: Update clock
> definitions
> 
> Hi Biju,
> 
> On Fri, Jun 18, 2021 at 11:58 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Update clock definitions as per the RZG2L_clock_list(Rev.02) manual.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/include/dt-bindings/clock/r9a07g044-cpg.h
> > +++ b/include/dt-bindings/clock/r9a07g044-cpg.h
> 
> > +#define R9A07G044_USB_SCLK             73
> 
> It looks like USB_SCLK cannot be gated, but is driven directly from
> OSCCLK, so I think it should be left out, and the DTS should just
> reference R9A07G044_OSCCLK

OK. Agreed, will remove this.

> 
> > +#define R9A07G044_ETH0_CLK_AXI         74
> > +#define R9A07G044_ETH0_CLK_CHI         75
> > +#define R9A07G044_ETH0_REFCLK          76
> > +#define R9A07G044_ETH1_CLK_AXI         77
> > +#define R9A07G044_ETH1_CLK_CHI         78
> > +#define R9A07G044_ETH1_REFCLK          79
> 
> According to the Hardware User's Manual, ETH0_REFCLK and  ETH1_REFCLK
> cannot be gated (see the note for CPG_CLKMON_ETH), so I think it should be
> left out, and the DTS should just reference R9A07G044_CLK_HP.

OK. Agreed. Will remove this.
> 
> The rest of the clocks look good to me.  Some are still missing, but they
> can be added later.
> 
> I do think we need a separate list of definitions for resets.  While
> simple modules like SCIF and I2C have a one-to-one mapping from clock bits
> to reset bits for, this is not the case for all modules.
> E.g. SDHI has 4 clocks per instance, but only a single reset signal per
> instance, while CANFD has a single clock, but two reset signals.


OK, Agreed. We will list separate definitions for resets like,

#define R9A07G044_RST_SDHI0		X1
#define R9A07G044_RST_SDHI1		X2
#define R9A07G044_RST_CAN		X3

Clk definitions

	DEF_MOD("sdhi0_imclk",	R9A07G044_SDHI0_IMCLK,
				CLK_SD0_DIV4,
				0x554, BIT(0)),
	DEF_MOD("sdhi0_imclk2",	R9A07G044_SDHI0_IMCLK2,
				CLK_SD0_DIV4,
				0x554, BIT(1)),
	DEF_MOD("sdhi0_clk_hs",	R9A07G044_SDHI0_CLK_HS,
				R9A07G044_CLK_SD0,
				0x554, BIT(2),
	DEF_MOD("sdhi0_aclk",	R9A07G044_SDHI0_ACLK,
				R9A07G044_CLK_P1,
				0x554, BIT(3)),


Reset definitions
--------------------
	DEF_RST("sdhi0_RST",	R9A07G044_RST_SDHI0,
				0x854, BIT(0)),


And DTS instantiate both reset and clock entries.

Is it ok to you? What is your thoughts on this?

Regards,
Biju



> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
>                                 -- Linus Torvalds