Since the gfxoff is always in dynamic switch, i do not think the status reported to user is reliable. It means user was told the gfx is on but actually it may switches to gfxoff already. Regards, Evan ________________________________ From: amd-gfx on behalf of Rex Zhu Sent: Sunday, July 29, 2018 7:42:27 PM To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Zhu, Rex Subject: [PATCH 3/3] drm/amd/pp: Add gfx power status check support on Rv/Vega12 As gfx off is supported on Rv/Vega12, so this check is helpful and necessary when visit gfx regesiter via mmio. Signed-off-by: Rex Zhu --- drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 10 +++++++ drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 31 +++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c index 26d130a..da1be82 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c @@ -296,6 +296,15 @@ static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) return false; } +static bool smu10_is_hw_ip_on(struct pp_hwmgr *hwmgr, + enum amd_ip_block_type client) +{ + if (client == AMD_IP_BLOCK_TYPE_GFX) + return smu10_is_gfx_on(hwmgr); + else /* for other ip, to do */ + return true; +} + static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) { struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); @@ -1187,6 +1196,7 @@ static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) .smus_notify_pwe = smu10_smus_notify_pwe, .display_clock_voltage_request = smu10_display_clock_voltage_request, .powergate_gfx = smu10_gfx_off_control, + .is_hw_ip_on = smu10_is_hw_ip_on, }; int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c index 0789d64..ee44300 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c @@ -45,7 +45,7 @@ #include "ppinterrupt.h" #include "pp_overdriver.h" #include "pp_thermal.h" - +#include "soc15_common.h" static int vega12_force_clock_level(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask); @@ -2320,6 +2320,34 @@ static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, return 0; } +/* GFX HW Power Status can be queried from bits [1:0] of MP1_SMN_EXT_SCRATCH0 + * 2'b00 GFX is OFF + * 2'b01 Transitioning out of GFXOFF state + * 2'b10 GFX is ON + * 2'b11 Transitioning into GFXOFF state +*/ + +static bool vega12_is_gfx_on(struct pp_hwmgr *hwmgr) +{ + uint32_t tmp; + struct amdgpu_device *adev = hwmgr->adev; + + tmp = RREG32_SOC15(MP1, 0, mmMP1_SMN_EXT_SCRATCH0); + if (tmp == 1 || tmp == 2) + return true; + else + return false; +} + +static bool vega12_is_hw_ip_on(struct pp_hwmgr *hwmgr, + enum amd_ip_block_type client) +{ + if (client == AMD_IP_BLOCK_TYPE_GFX) + return vega12_is_gfx_on(hwmgr); + else /* for other ip, to do */ + return true; +} + static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr) { struct vega12_hwmgr *data = @@ -2402,6 +2430,7 @@ static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) .register_irq_handlers = smu9_register_irq_handlers, .start_thermal_controller = vega12_start_thermal_controller, .powergate_gfx = vega12_gfx_off_control, + .is_hw_ip_on = vega12_is_hw_ip_on, }; int vega12_hwmgr_init(struct pp_hwmgr *hwmgr) -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx