From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A60C47089 for ; Wed, 26 May 2021 07:18:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68A1861402 for ; Wed, 26 May 2021 07:18:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233011AbhEZHTu (ORCPT ); Wed, 26 May 2021 03:19:50 -0400 Received: from muru.com ([72.249.23.125]:60568 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233030AbhEZHTq (ORCPT ); Wed, 26 May 2021 03:19:46 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 581CE80AE; Wed, 26 May 2021 07:18:19 +0000 (UTC) Date: Wed, 26 May 2021 10:18:10 +0300 From: Tony Lindgren To: Rob Herring Cc: Sven Peter , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, * Rob Herring [210525 18:09]: > I would do a single node per mmio region with the register offset (or > offset / 4) being the clock id. This can still support new SoCs easily > if you have a fallback compatible. If you want/need to get all the > clocks, just walk the DT 'clocks' properties and extract all the IDs. I mostly agree.. Except I'd also leave out the artificial clock ID and just use real register offsets from the clock controller base instead. So a single clock controller node for each MMIO range, then set #clock=cells = <1>. Then the binding follows what we have for the interrupts-extended binding for example. If the clock controller optionally needs some data in the dts, that can be added to the clock controller node. Or it can be driver internal built-in data. If the data for dts can be described in a generic way, even better :) This would make the consumer interface look like below with a clock controller node and register offset from it: clocks = <&clock_controller1 0x1234>; Regards, Tony From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C17EC2B9F7 for ; Wed, 26 May 2021 07:20:08 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E15FF61402 for ; Wed, 26 May 2021 07:20:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E15FF61402 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=atomide.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=YaSkOTYsF4WWgmjtyqJWhjzTKGo2bt6KgPKQcCt1jlk=; b=b706/wW67e9FTS N4fMjIhDidyajgVNWiPP4tSfZun7ymREBQ0ISSbvCHoLWLrMmfqER43qauuuWRAHXeCO9h9PHd/BT t/cvPkYlYGTC5xR8Xs4Vbtv3K7x7u7bY0KAuaFRhFKHbtzOr3vhNrejJV1uqUzBvpCMxrpuef7BUx Rq4ik8RKU1UoocC4F5ad1SiDrSl8IJotqDYE5hjGMQLfnLdV6wrAs9YkP+C96TaAgYmNEyApL9gfN G+JwQvTVYkNVAt1HLxhMKLePH5O2qpLumhGS0G2yzIRkeBskm67d67XFOKFmjdI4UdgxjxscndE1e ZLKKWr5Fo/vNahR7J6cA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llno3-00Byxw-Ua; Wed, 26 May 2021 07:18:20 +0000 Received: from muru.com ([72.249.23.125]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llnnz-00ByvG-Sh for linux-arm-kernel@lists.infradead.org; Wed, 26 May 2021 07:18:17 +0000 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id 581CE80AE; Wed, 26 May 2021 07:18:19 +0000 (UTC) Date: Wed, 26 May 2021 10:18:10 +0300 From: Tony Lindgren To: Rob Herring Cc: Sven Peter , devicetree@vger.kernel.org, linux-clk , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Hector Martin , Michael Turquette , Stephen Boyd , Mark Kettenis , Arnd Bergmann Subject: Re: [PATCH 0/3] Apple M1 clock gate driver Message-ID: References: <20210524182745.22923-1-sven@svenpeter.dev> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210526_001816_013339_FB9C0B9C X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, * Rob Herring [210525 18:09]: > I would do a single node per mmio region with the register offset (or > offset / 4) being the clock id. This can still support new SoCs easily > if you have a fallback compatible. If you want/need to get all the > clocks, just walk the DT 'clocks' properties and extract all the IDs. I mostly agree.. Except I'd also leave out the artificial clock ID and just use real register offsets from the clock controller base instead. So a single clock controller node for each MMIO range, then set #clock=cells = <1>. Then the binding follows what we have for the interrupts-extended binding for example. If the clock controller optionally needs some data in the dts, that can be added to the clock controller node. Or it can be driver internal built-in data. If the data for dts can be described in a generic way, even better :) This would make the consumer interface look like below with a clock controller node and register offset from it: clocks = <&clock_controller1 0x1234>; Regards, Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel