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bh=MT/fH3L17p/XDLnDLYuSCKrDvuIFWCZgm1euP6y01oQ=; b=UCMcv+I/SU9MtD/a1DjpAcS3SNCUfomzLBvA1opWGXajhKW3+87YhSAjjIVk1oII6z9y0X 87LpKBstKlSeo4ulppeGHE55gQp0nfxiD6MUayF1zgIXyqlUDeXJsYcTtRSebwcs4B41Zt s2Ke5GCzgkWLAhHsSVMXHFohoIyL4Pg= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-159-k9qOxwenPI2hHBzjOX1wJQ-1; Mon, 13 Sep 2021 08:13:41 -0400 X-MC-Unique: k9qOxwenPI2hHBzjOX1wJQ-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id CDD381084689; Mon, 13 Sep 2021 12:13:39 +0000 (UTC) Received: from localhost (unknown [10.39.195.28]) by smtp.corp.redhat.com (Postfix) with ESMTP id F2B48189BB; Mon, 13 Sep 2021 12:13:34 +0000 (UTC) Date: Mon, 13 Sep 2021 13:13:33 +0100 From: Stefan Hajnoczi To: Jag Raman Subject: Re: [PATCH RFC server v2 06/11] vfio-user: handle PCI config space accesses Message-ID: References: <5f371fa15eb347317ce9ce56a329a24c713129e0.1630084211.git.jag.raman@oracle.com> <23A4AF68-0D0C-475F-B522-6ADAC0CED2AC@oracle.com> MIME-Version: 1.0 In-Reply-To: <23A4AF68-0D0C-475F-B522-6ADAC0CED2AC@oracle.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=stefanha@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="wO5+dVZQnfKUJQ0v" Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=stefanha@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.398, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Elena Ufimtseva , John Johnson , "thuth@redhat.com" , "swapnil.ingle@nutanix.com" , "john.levon@nutanix.com" , "philmd@redhat.com" , qemu-devel , Alex Williamson , =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , "thanos.makatos@nutanix.com" , "alex.bennee@linaro.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --wO5+dVZQnfKUJQ0v Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Sep 10, 2021 at 04:22:56PM +0000, Jag Raman wrote: >=20 >=20 > > On Sep 9, 2021, at 3:27 AM, Stefan Hajnoczi wrote= : > >=20 > > On Fri, Aug 27, 2021 at 01:53:25PM -0400, Jagannathan Raman wrote: > >> +static ssize_t vfu_object_cfg_access(vfu_ctx_t *vfu_ctx, char * const= buf, > >> + size_t count, loff_t offset, > >> + const bool is_write) > >> +{ > >> + VfuObject *o =3D vfu_get_private(vfu_ctx); > >> + uint32_t pci_access_width =3D sizeof(uint32_t); > >> + size_t bytes =3D count; > >> + uint32_t val =3D 0; > >> + char *ptr =3D buf; > >> + int len; > >> + > >> + while (bytes > 0) { > >> + len =3D (bytes > pci_access_width) ? pci_access_width : bytes= ; > >> + if (is_write) { > >> + memcpy(&val, ptr, len); > >> + pci_default_write_config(PCI_DEVICE(o->pci_dev), > >> + offset, val, len); > >> + trace_vfu_cfg_write(offset, val); > >> + } else { > >> + val =3D pci_default_read_config(PCI_DEVICE(o->pci_dev), > >> + offset, len); > >> + memcpy(ptr, &val, len); > >=20 > > pci_default_read_config() returns a host-endian 32-bit value. This code > > looks wrong because it copies different bytes on big- and little-endian > > hosts. >=20 > I=E2=80=99ll collect more details on this one, trying to wrap my head aro= und it. >=20 > Concerning config space writes, it doesn=E2=80=99t look like we need to > perform any conversion as the store operation automatically happens > in the CPU=E2=80=99s native format when we do something like the followin= g: > PCIDevice->config[addr] =3D val; PCIDevice->config is uint8_t*. Endianness isn't an issue with single byte accesses. >=20 > Concerning config read, I observed that pci_default_read_config() > performs le32_to_cpu() conversion. May be we should not rely on > it doing the conversion. Yes, ->config_read() returns a host-endian 32-bit value and ->config_write() receives a host-endian 32-bit value (it has a bit-shifting loop that implicitly handles endianness conversion). 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