From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E5BFC433FE for ; Fri, 17 Sep 2021 12:54:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3BBF760F6D for ; Fri, 17 Sep 2021 12:54:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3BBF760F6D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA9BC6EC74; Fri, 17 Sep 2021 12:53:59 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA1F86EC6C; Fri, 17 Sep 2021 12:53:58 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="219603882" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="219603882" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 05:53:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="517126322" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 17 Sep 2021 05:53:55 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 17 Sep 2021 15:53:54 +0300 Date: Fri, 17 Sep 2021 15:53:54 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, manasi.d.navare@intel.com Subject: Re: [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH,LOW} for 128b/132b Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: > There's a new register pair for 128b/132b mode where you need to set the > pixel clock in Hz. > > v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper > > Bspec: 54128 > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d104441344c0..97af19fd9780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > clear_act_sent(encoder, pipe_config); > > + if (intel_dp_is_uhbr(pipe_config)) { > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->hw.adjusted_mode; > + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); > + > + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); > + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); > + } > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > -- > 2.30.2 -- Ville Syrjälä Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85434C433F5 for ; Fri, 17 Sep 2021 12:54:00 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4DE29610C7 for ; Fri, 17 Sep 2021 12:54:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4DE29610C7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B778D6EC6C; Fri, 17 Sep 2021 12:53:59 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA1F86EC6C; Fri, 17 Sep 2021 12:53:58 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10109"; a="219603882" X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="219603882" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Sep 2021 05:53:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,301,1624345200"; d="scan'208";a="517126322" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.171]) by orsmga001.jf.intel.com with SMTP; 17 Sep 2021 05:53:55 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 17 Sep 2021 15:53:54 +0300 Date: Fri, 17 Sep 2021 15:53:54 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, manasi.d.navare@intel.com Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Patchwork-Hint: comment Subject: Re: [Intel-gfx] [PATCH v3 12/13] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Sep 09, 2021 at 03:52:04PM +0300, Jani Nikula wrote: > There's a new register pair for 128b/132b mode where you need to set the > pixel clock in Hz. > > v2: Fix UHBR rate check, use intel_dp_is_uhbr() helper > > Bspec: 54128 > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index d104441344c0..97af19fd9780 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > > clear_act_sent(encoder, pipe_config); > > + if (intel_dp_is_uhbr(pipe_config)) { > + const struct drm_display_mode *adjusted_mode = > + &pipe_config->hw.adjusted_mode; > + u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); > + > + intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); > + intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), > + TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); > + } > + > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > -- > 2.30.2 -- Ville Syrjälä Intel