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Mon, 20 Sep 2021 17:36:52 +1000 (AEST) Date: Mon, 20 Sep 2021 17:36:23 +1000 From: David Gibson To: =?iso-8859-1?Q?C=E9dric?= Le Goater Subject: Re: [PATCH v4 4/4] target/ppc: Fix 64-bit decrementer Message-ID: References: <20210920061203.989563-1-clg@kaod.org> <20210920061203.989563-5-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="B2DYzSAA8ThEP4IU" Content-Disposition: inline In-Reply-To: <20210920061203.989563-5-clg@kaod.org> Received-SPF: pass client-ip=2401:3900:2:1::2; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Fernando Fujita Pires , qemu-ppc@nongnu.org, Greg Kurz , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --B2DYzSAA8ThEP4IU Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 20, 2021 at 08:12:03AM +0200, C=E9dric Le Goater wrote: > The current way the mask is built can overflow with a 64-bit decrementer. > Use sextract64() to extract the signed values and remove the logic to > handle negative values which has become useless. >=20 > Cc: Luis Fernando Fujita Pires > Fixes: a8dafa525181 ("target/ppc: Implement large decrementer support for= TCG") > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson LGTM, but not applying because of the comments on 3/4. > --- > hw/ppc/ppc.c | 20 +++++++++----------- > 1 file changed, 9 insertions(+), 11 deletions(-) >=20 > diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c > index b813ef732ec1..f5d012f860af 100644 > --- a/hw/ppc/ppc.c > +++ b/hw/ppc/ppc.c > @@ -821,14 +821,12 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, u= int64_t *nextp, > CPUPPCState *env =3D &cpu->env; > ppc_tb_t *tb_env =3D env->tb_env; > uint64_t now, next; > - bool negative; > + int64_t signed_value; > + int64_t signed_decr; > =20 > /* Truncate value to decr_width and sign extend for simplicity */ > - value &=3D ((1ULL << nr_bits) - 1); > - negative =3D !!(value & (1ULL << (nr_bits - 1))); > - if (negative) { > - value |=3D (0xFFFFFFFFULL << nr_bits); > - } > + signed_value =3D sextract64(value, 0, nr_bits); > + signed_decr =3D sextract64(decr, 0, nr_bits); > =20 > trace_ppc_decr_store(nr_bits, decr, value); > =20 > @@ -850,16 +848,16 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, u= int64_t *nextp, > * On MSB edge based DEC implementations the MSB going from 0 -> 1 t= riggers > * an edge interrupt, so raise it here too. > */ > - if ((value < 3) || > - ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || > - ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative > - && !(decr & (1ULL << (nr_bits - 1))))) { > + if ((signed_value < 3) || > + ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && signed_value < 0)= || > + ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && signed_value = < 0 > + && signed_decr >=3D 0)) { > (*raise_excp)(cpu); > return; > } > =20 > /* On MSB level based systems a 0 for the MSB stops interrupt delive= ry */ > - if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { > + if (signed_value >=3D 0 && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL= )) { > (*lower_excp)(cpu); > } > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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