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From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM
Date: Thu, 28 Apr 2022 14:31:33 +0100	[thread overview]
Message-ID: <YmqXNcLthPfeBuuV@lakrids> (raw)
In-Reply-To: <20220426181704.2583494-7-broonie@kernel.org>

On Tue, Apr 26, 2022 at 07:16:58PM +0100, Mark Brown wrote:
> The architecture reference manual refers to the field in bits 23:20 of
> ID_AA64ISAR0_EL1 with the name "atomic" but the kernel defines for this
> bitfield use the name "atomics". Bring the two into sync to make it easier
> to cross reference with the specification.
> 
> Signed-off-by: Mark Brown <broonie@kernel.org>

Acked-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/sysreg.h                | 2 +-
>  arch/arm64/kernel/cpufeature.c                 | 6 +++---
>  arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 331e2521a81a..0bb259ec6ee8 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -749,7 +749,7 @@
>  #define ID_AA64ISAR0_SM3_SHIFT		36
>  #define ID_AA64ISAR0_SHA3_SHIFT		32
>  #define ID_AA64ISAR0_RDM_SHIFT		28
> -#define ID_AA64ISAR0_ATOMICS_SHIFT	20
> +#define ID_AA64ISAR0_ATOMIC_SHIFT	20
>  #define ID_AA64ISAR0_CRC32_SHIFT	16
>  #define ID_AA64ISAR0_SHA2_SHIFT		12
>  #define ID_AA64ISAR0_SHA1_SHIFT		8
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index d72c4b4d389c..18833fe6d148 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -200,7 +200,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
> -	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
> +	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMIC_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
>  	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
> @@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
>  		.matches = has_cpuid_feature,
>  		.sys_reg = SYS_ID_AA64ISAR0_EL1,
> -		.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
> +		.field_pos = ID_AA64ISAR0_ATOMIC_SHIFT,
>  		.field_width = 4,
>  		.sign = FTR_UNSIGNED,
>  		.min_field_value = 2,
> @@ -2520,7 +2520,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
> -	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
> +	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
>  	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
> diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
> index 5ad626527d41..63a114b9b2ed 100644
> --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
> +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
> @@ -163,7 +163,7 @@
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \
> -	ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS) | \
> +	ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMIC) | \
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \
>  	ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \
> -- 
> 2.30.2
> 

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  reply	other threads:[~2022-04-28 13:38 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-26 18:16 [PATCH v5 00/12] arm64: Automatic system register definition generation Mark Brown
2022-04-26 18:16 ` [PATCH v5 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
2022-04-26 18:16 ` [PATCH v5 02/12] arm64/mte: Make TCF0 naming and field values more standard Mark Brown
2022-04-26 18:16 ` [PATCH v5 03/12] arm64/mte: Make TCF field values and naming " Mark Brown
2022-04-26 18:16 ` [PATCH v5 04/12] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-26 18:16 ` [PATCH v5 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 Mark Brown
2022-04-26 18:16 ` [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Mark Brown
2022-04-28 13:31   ` Mark Rutland [this message]
2022-04-26 18:16 ` [PATCH v5 07/12] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-26 18:17 ` [PATCH v5 08/12] arm64: Add sysreg header generation scripting Mark Brown
2022-04-26 18:17 ` [PATCH v5 09/12] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-26 18:17 ` [PATCH v5 10/12] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 11/12] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 12/12] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-05-03 11:28 ` [PATCH v5 00/12] arm64: Automatic system register definition generation Catalin Marinas
2022-05-03 12:58   ` Mark Rutland
2022-05-03 16:32   ` Mark Brown

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