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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Tue, 23 Apr 2019 12:28:11 -0700
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Subject: Re: [Qemu-devel] [PATCH 12/38] tcg: Add gvec expanders for variable
 shift
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To: David Hildenbrand <david@redhat.com>, qemu-devel@nongnu.org

On 4/23/19 12:04 PM, David Hildenbrand wrote:
> In order to use this on s390x for VECTOR ELEMENT SHIFT, like
> 
> +static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
> +{
> +    const uint8_t es = get_field(s->fields, m4);
> +    const uint8_t v1 = get_field(s->fields, v1);
> +    const uint8_t v2 = get_field(s->fields, v2);
> +    const uint8_t v3 = get_field(s->fields, v3);
> +
> +    if (es > ES_64) {
> +        gen_program_exception(s, PGM_SPECIFICATION);
> +        return DISAS_NORETURN;
> +    }
> +
> +    switch (s->fields->op2) {
> +    case 0x70:
> +        gen_gvec_fn_3(shlv, es, v1, v2, v3);
> +        break;
> +    case 0x7a:
> +        gen_gvec_fn_3(sarv, es, v1, v2, v3);
> +        break;
> +    case 0x78:
> +        gen_gvec_fn_3(shrv, es, v1, v2, v3);
> +        break;
> +    default:
> +        g_assert_not_reached();
> +    }
> +
> +    return DISAS_NEXT;
> +}
> 
> We need to mask of invalid bits from the shift. Can that be added?

Yes, I do exactly this in patch 31 for target/ppc.


r~