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[75.142.250.213]) by smtp.gmail.com with ESMTPSA id l13sm6440861qtv.82.2020.09.05.13.39.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Sep 2020 13:39:52 -0700 (PDT) Subject: Re: [PATCH v1 03/12] fpga: expose max10 flash update counts in sysfs To: Russ Weight , mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org, linux-kernel@vger.kernel.org Cc: lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com, matthew.gerlach@intel.com References: <20200904235305.6254-1-russell.h.weight@intel.com> <20200904235305.6254-4-russell.h.weight@intel.com> From: Tom Rix Message-ID: Date: Sat, 5 Sep 2020 13:39:50 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: <20200904235305.6254-4-russell.h.weight@intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/4/20 4:52 PM, Russ Weight wrote: > Extend the MAX10 BMC Security Engine driver to provide a > handler to expose the flash update count for the FPGA user > image. > > Signed-off-by: Russ Weight > Reviewed-by: Wu Hao > --- > drivers/fpga/intel-m10-bmc-secure.c | 32 +++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c > index 1f86bfb694b4..b824790e43aa 100644 > --- a/drivers/fpga/intel-m10-bmc-secure.c > +++ b/drivers/fpga/intel-m10-bmc-secure.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > > struct m10bmc_sec { > @@ -99,7 +100,38 @@ SYSFS_GET_REH(bmc, BMC_REH_ADDR) > SYSFS_GET_REH(sr, SR_REH_ADDR) > SYSFS_GET_REH(pr, PR_REH_ADDR) > > +#define FLASH_COUNT_SIZE 4096 This seems too high at most it should be 64. > +#define USER_FLASH_COUNT 0x17ffb000 Why shouldn't this be in intel-m10-bmc.h ? > + > +static int get_qspi_flash_count(struct ifpga_sec_mgr *imgr) what does 'qspi' mean ? unless there are going to be several *flash_count's consider removing this substring. > +{ > + struct m10bmc_sec *sec = imgr->priv; > + unsigned int stride = regmap_get_reg_stride(sec->m10bmc->regmap); > + unsigned int cnt, num_bits = FLASH_COUNT_SIZE * 8; > + u8 *flash_buf; > + int ret; > + > + flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL); > + if (!flash_buf) > + return -ENOMEM; > + > + ret = m10bmc_raw_bulk_read(sec->m10bmc, USER_FLASH_COUNT, flash_buf, > + FLASH_COUNT_SIZE / stride); > + if (ret) { > + dev_err(sec->dev, "%s failed to read %d\n", __func__, ret); > + goto exit_free; > + } > + > + cnt = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits); Simplify ret = num_bits... > + > +exit_free: > + kfree(flash_buf); > + > + return ret ? : cnt; Then simplify return ret; Tom > +} > + > static const struct ifpga_sec_mgr_ops m10bmc_iops = { > + .user_flash_count = get_qspi_flash_count, > .bmc_root_entry_hash = get_bmc_root_entry_hash, > .sr_root_entry_hash = get_sr_root_entry_hash, > .pr_root_entry_hash = get_pr_root_entry_hash,