From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751478AbdB1G2Z (ORCPT ); Tue, 28 Feb 2017 01:28:25 -0500 Received: from mga09.intel.com ([134.134.136.24]:24207 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751134AbdB1G2X (ORCPT ); Tue, 28 Feb 2017 01:28:23 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,216,1484035200"; d="scan'208";a="62713628" Date: Mon, 27 Feb 2017 16:04:59 -0800 (PST) From: matthew.gerlach@linux.intel.com X-X-Sender: mgerlach@mgerlach-VirtualBox To: Moritz Fischer cc: Alan Tull , "Nadathur, Sundar" , Yves Vandervennet , Jason Gunthorpe , linux-kernel , "linux-fpga@vger.kernel.org" , =?ISO-8859-15?Q?Marek_Va=A8ut?= Subject: Re: [RFC 7/8] fpga-region: add sysfs interface In-Reply-To: Message-ID: References: <20170215203734.GC5531@obsidianresearch.com> <20170218023010.GA8244@live.com> <1CC272501B5BC543A05DB90AA509DED50AF5EC@fmsmsx122.amr.corp.intel.com> <20170218204509.GA32544@live.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 27 Feb 2017, Moritz Fischer wrote: > Alan, > > On Mon, Feb 27, 2017 at 12:09 PM, Alan Tull wrote: > > >> First case: embedded FPGA. The hardware has one FPGA. The image is >> designed for a specific board, so there's no problem including the >> enumeration in the image. > > Agreed. > >> Second case: embedded FPGA + a PCIe FPGA. The image will be specific >> as to whether it goes into the embedded FPGA or the PCIe one. > > Agreed. > > >> Third case: multiple PCIe FPGAs. The enumeration base will be the >> PCIe bus of the individual FPGA. If the FPGAs don't have unique pin >> connections, then the images could go on any of the PCie FPGAs. If >> there are unique pin connections, then the image will be specific to >> the FPGA and having the enumeration data in the image is that much >> more helpful for keeping things straight. Part of the header could >> specify which specific FPGA it should go on if it is restricted. > > Agreed. > >> Of course if the FPGAs have > 1 PR regions, most FPGA architectures do >> not have relocatable images so those images will be specific for the >> PR region but not specific to the FPGA except as otherwise noted >> above. >> >> So again, including enumeration data in the bitstream should work >> unless I'm missing something. What am I missing here? > > If you enumeration base is sufficiently smart, I suppose that can work. > What you'd probably want is some sort of extension to the platform bus? I think there is merit it considering the platform bus as part of the overal enumeration strategy. When using device trees, the platform bus is involved. I have also seen other folks enumerate over a platform bus based on data in a format other than device tree. I have experimented with instantiating platform devices from my pcie driver, but I didn't completely work, which could be related to using a fairly old 3.10 kernel. Matthew Gerlach > > I really need to take another look at how non-dt systems enumerate to > give better feedback on this. > > Cheers, > > Moritz > -- > To unsubscribe from this list: send the line "unsubscribe linux-fpga" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >