From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33461) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yse6R-000529-HE for qemu-devel@nongnu.org; Wed, 13 May 2015 17:22:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yse6M-0005HY-IL for qemu-devel@nongnu.org; Wed, 13 May 2015 17:22:07 -0400 Received: from eddie.linux-mips.org ([148.251.95.138]:47495 helo=cvs.linux-mips.org) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yse6M-0005HA-AI for qemu-devel@nongnu.org; Wed, 13 May 2015 17:22:02 -0400 Received: (from localhost user: 'macro', uid#1010) by eddie.linux-mips.org with ESMTP id S27013241AbbEMVV6yHtuB (ORCPT ); Wed, 13 May 2015 23:21:58 +0200 Date: Wed, 13 May 2015 22:21:58 +0100 (BST) Sender: "Maciej W. Rozycki" From: "Maciej W. Rozycki" In-Reply-To: <5553BB40.7050706@imgtec.com> Message-ID: References: <1431531457-17127-1-git-send-email-yongbok.kim@imgtec.com> <1431531457-17127-3-git-send-email-yongbok.kim@imgtec.com> <5553A5C4.6030902@twiddle.net> <5553ACF2.7050708@twiddle.net> <5553BB40.7050706@imgtec.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Subject: Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: Yongbok Kim , peter.maydell@linaro.org, qemu-devel@nongnu.org, afaerber@suse.de, Richard Henderson On Wed, 13 May 2015, Leon Alrae wrote: > > Certainly we do. It's all in softmmu_template.h. > > I believe the problem is that MSA vector register's size is 16-bytes > (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store > is supposed to be atomic. Not really AFAICT. Here's what the specification says[1]: "The vector load instruction is atomic at the element level with no guaranteed ordering among elements, i.e. each element load is an atomic operation issued in no particular order with respect to the element's vector position." and[2]: "The vector store instruction is atomic at the element level with no guaranteed ordering among elements, i.e. each element store is an atomic operation issued in no particular order with respect to the element's vector position." so you only need to get atomic up to 8 bytes (with LD.D and ST.D, less with the narrower vector elements), and that looks supported to me. References: [1] "MIPS Architecture for Programmers, Volume IV-j: The MIPS32 SIMD Architecture Module", Revision 1.07, MIPS Technologies, Inc., Document Number: MD00866, October 2, 2013, p. 314 [2] same, p. 414 Maciej