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From: Manish Jaggi <manish.jaggi@cavium.com>
To: xen-devel@lists.xenproject.org, julien.grall@arm.com,
	sstabellini@kernel.org, marc.zyngier@arm.com,
	andre.przywara@arm.com
Cc: manish.jaggi@cavium.com
Subject: [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers
Date: Tue, 27 Mar 2018 14:37:21 +0530	[thread overview]
Message-ID: <b61e9bd91a6d08a9c14d62f9820d098feed27f50.1522135597.git.manish.jaggi@cavium.com> (raw)
In-Reply-To: <cover.1522135597.git.manish.jaggi@cavium.com>

This patch is ported to xen from linux commit:
eab0b2dc4f6f34147e3d10da49ab8032e15dbea0
(KVM: arm64: vgic-v3: Add misc Group-0 handlers)

A number of Group-0 registers can be handled by the same accessors
as that of Group-1, so let's add the required system register encodings
and catch them in the dispatching function.

Signed-off-by: Manish Jaggi <manish.jaggi@cavium.com>
---
 xen/arch/arm/arm64/vgic-v3-sr.c     | 7 +++++++
 xen/include/asm-arm/arm64/sysregs.h | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/xen/arch/arm/arm64/vgic-v3-sr.c b/xen/arch/arm/arm64/vgic-v3-sr.c
index d854b1070d..201194c713 100644
--- a/xen/arch/arm/arm64/vgic-v3-sr.c
+++ b/xen/arch/arm/arm64/vgic-v3-sr.c
@@ -793,30 +793,37 @@ bool vgic_v3_handle_cpuif_access(struct cpu_user_regs *regs)
         vreg_emulate_igrpen1(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_IAR0_EL1:
     case HSR_SYSREG_ICC_IAR1_EL1:
         vreg_emulate_iar(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_EOIR0_EL1:
     case HSR_SYSREG_ICC_EOIR1_EL1:
         vreg_emulate_eoi(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(0):
     case HSR_SYSREG_ICC_AP1Rn_EL1(0):
         vreg_emulate_apxr0(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(1):
     case HSR_SYSREG_ICC_AP1Rn_EL1(1):
         vreg_emulate_apxr1(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(2):
     case HSR_SYSREG_ICC_AP1Rn_EL1(2):
         vreg_emulate_apxr2(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_AP0Rn_EL1(3):
     case HSR_SYSREG_ICC_AP1Rn_EL1(3):
         vreg_emulate_apxr3(regs, hsr);
         break;
 
+    case HSR_SYSREG_ICC_HPPIR0_EL1:
     case HSR_SYSREG_ICC_HPPIR1_EL1:
         vreg_emulate_hppir1(regs, hsr);
         break;
diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h
index 8a4f5b45cb..6d346d84db 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -97,6 +97,10 @@
 #define HSR_SYSREG_ICC_HPPIR1_EL1 HSR_SYSREG(3,0,c12,c12,2)
 #define HSR_SYSREG_ICC_BPR0_EL1   HSR_SYSREG(3,0,c12,c8,3)
 #define HSR_SYSREG_ICC_IGRPEN0_EL1 HSR_SYSREG(3,0,c12,c12,6)
+#define HSR_SYSREG_ICC_IAR0_EL1   HSR_SYSREG(3,0,c12,c8,0)
+#define HSR_SYSREG_ICC_EOIR0_EL1  HSR_SYSREG(3,0,c12,c8,1)
+#define HSR_SYSREG_ICC_HPPIR0_EL1 HSR_SYSREG(3,0,c12,c8,2)
+#define HSR_SYSREG_ICC_AP0Rn_EL1(n) HSR_SYSREG(3,0,c12,c8,4|n)
 #define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
 
 #define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-- 
2.14.1


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  parent reply	other threads:[~2018-03-27  9:09 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-27  9:07 [PATCH v2 00/17] arm64: Mediate access to GICv3 sysregs at EL2 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 01/17] arm: Placeholder for handling Group0/1 traps Manish Jaggi
2018-03-27 10:01   ` Marc Zyngier
2018-03-27 10:10     ` Manish Jaggi
2018-03-27 10:22       ` Marc Zyngier
2018-03-27 20:16         ` Stefano Stabellini
2018-03-28  0:48           ` Julien Grall
2018-03-28  3:48             ` Manish Jaggi
2018-04-03 15:33               ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 02/17] arm64: vgic-v3: Add ICV_BPR1_EL1 handler Manish Jaggi
2018-03-27 10:30   ` Marc Zyngier
2018-03-27 10:35     ` Manish Jaggi
2018-03-27 10:45       ` Marc Zyngier
2018-03-27 10:56         ` Manish Jaggi
2018-03-27 11:05           ` Marc Zyngier
2018-03-27 11:07             ` Manish Jaggi
2018-03-27 11:11               ` Marc Zyngier
2018-03-27 11:15                 ` Manish Jaggi
2018-03-27 11:25                   ` Marc Zyngier
2018-03-27 11:27                     ` Manish Jaggi
2018-03-27 11:38                       ` Marc Zyngier
2018-03-28  3:51                         ` Manish Jaggi
2018-04-03 15:59                           ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 03/17] arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 04/17] arm64: Add accessors for the ICH_APxRn_EL2 registers Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 05/17] Expose ich_read/write_lr in vgic-v3-sr.c Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 06/17] arm64: Add ICV_IAR1_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 07/17] arm64: vgic-v3: Add ICV_EOIR1_EL1 handler Manish Jaggi
2018-03-27 10:18   ` Marc Zyngier
2018-04-02 11:03     ` Manish Jaggi
2018-04-02 11:17       ` Manish Jaggi
2018-04-05  9:40         ` Julien Grall
2018-04-05 19:53           ` Stefano Stabellini
2018-04-06  8:37           ` Manish Jaggi
2018-04-11 14:16             ` Julien Grall
2018-03-27  9:07 ` [PATCH v2 08/17] arm64: vgic-v3: Add ICV_AP1Rn_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 09/17] arm64: vgic-v3: Add ICV_HPPIR1_EL1 handler Manish Jaggi
2018-03-27 10:56   ` Marc Zyngier
2018-03-27 11:02     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 10/17] arm64: vgic-v3: Add ICV_BPR0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 11/17] arm64: vgic-v3: Add ICV_IGRPEN0_EL1 handler Manish Jaggi
2018-03-27  9:07 ` Manish Jaggi [this message]
2018-03-27 10:58   ` [PATCH v2 12/17] arm64: vgic-v3: Add misc Group-0 handlers Marc Zyngier
2018-03-27 11:01     ` Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 13/17] arm64: cputype: Add MIDR values for Cavium ThunderX1 CPU family Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 14/17] arm64: Add config for Cavium Thunder erratum 30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 15/17] arm: Hook workaround handler from traps.c based on Cavium workaround_30115 Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 16/17] arm64: if trapping a write-to-read-only GICv3 access inject Undef exception in guest Manish Jaggi
2018-03-27  9:07 ` [PATCH v2 17/17] arm64: if trapping a read-from-write-only GICv3 access inject undef " Manish Jaggi

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