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From: Dmitry Osipenko <digetx@gmail.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH RE-SEND] clk: tegra: Don't enable already enabled PLLs
Date: Wed, 27 Feb 2019 18:15:04 +0300	[thread overview]
Message-ID: <b64760b5-0d37-ae05-9c8e-9e6d47293c92@gmail.com> (raw)
In-Reply-To: <20190224153222.8142-1-digetx@gmail.com>

24.02.2019 18:32, Dmitry Osipenko пишет:
> Initially Common Clock Framework isn't aware of the clock-enable status,
> this results in enabling of clocks that were enabled by bootloader. This
> is not a big deal for a regular clock-gates, but for PLL's it may have
> some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
> clock) may result in extra long period of PLL re-locking.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---

Peter (and everyone else), yours r-b and ACK will be appreciated since you kinda already took a look at this patch in the past and were okay with it (IIRC, we had some brief discussion on the #tegra IRC a few months ago), thanks. 

  reply	other threads:[~2019-02-27 15:15 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-24 15:32 [PATCH RE-SEND] clk: tegra: Don't enable already enabled PLLs Dmitry Osipenko
2019-02-27 15:15 ` Dmitry Osipenko [this message]
2019-03-04  8:18   ` Peter De Schrijver
2019-03-04  8:18     ` Peter De Schrijver
2019-03-04 13:42     ` Dmitry Osipenko
2019-04-14 15:27       ` Dmitry Osipenko

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