From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31131C4707F for ; Thu, 27 May 2021 06:17:52 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2989460249 for ; Thu, 27 May 2021 06:17:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2989460249 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6A66E81658; Thu, 27 May 2021 08:17:49 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1622096269; bh=8wkBFMJ0L+BlodFpfjsB7ZWGuF2ACMQ27Id+g9c2tIo=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=PEk96dn/aopRXbFGUeCOsd3/dsZqbfZCJBSpl0/lTDt+5LL8dDmzyRqRcFzlUCVfD s/0Frs7w7LfFVIGbeWE4r7fqFSdvUYYgs/Pq+7si68vttqSYXDBsfs9zklUPf3VBFx 89Z4SrEZ0mPQTpD7dq3AOEWTiX3t5SRLB8l42K/OjyPorSa7Rfyi/R6aNJBJmeZb+t FXLYvuCO0zG7ARDQUn7sDZoQLhEedhP3NEBWRk6f/bhWR8SEGA88KXE2xM9hFheqZG 6sJLEh0wcXTOUGSf23a46/3tJlQB+IVwMRe3nlK82Lj+hPER2CBSrDFn4IY1/5kuvJ 3bV0Ut2sjlXSg== Received: by phobos.denx.de (Postfix, from userid 109) id BF74882E4A; Thu, 27 May 2021 08:17:47 +0200 (CEST) Received: from mout-u-107.mailbox.org (mout-u-107.mailbox.org [91.198.250.252]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0C1EF80C67 for ; Thu, 27 May 2021 08:17:45 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (smtp2.mailbox.org [80.241.60.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-107.mailbox.org (Postfix) with ESMTPS id 4FrHfx0BJKzQjBM; Thu, 27 May 2021 08:17:45 +0200 (CEST) Received: from smtp2.mailbox.org ([80.241.60.241]) by spamfilter04.heinlein-hosting.de (spamfilter04.heinlein-hosting.de [80.241.56.122]) (amavisd-new, port 10030) with ESMTP id NeLG0iXlafRR; Thu, 27 May 2021 08:17:42 +0200 (CEST) Subject: Re: [PATCH u-boot-marvell 4/5] serial: a37xx: Switch to XTAL clock when booting Linux kernel To: =?UTF-8?Q?Marek_Beh=c3=ban?= , u-boot@lists.denx.de Cc: =?UTF-8?Q?Pali_Roh=c3=a1r?= References: <20210525174242.27509-1-marek.behun@nic.cz> <20210525174242.27509-5-marek.behun@nic.cz> From: Stefan Roese Message-ID: Date: Thu, 27 May 2021 08:17:41 +0200 MIME-Version: 1.0 In-Reply-To: <20210525174242.27509-5-marek.behun@nic.cz> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-MBO-SPAM-Probability: X-Rspamd-Score: -6.68 / 15.00 / 15.00 X-Rspamd-Queue-Id: 20E721811 X-Rspamd-UID: 4c888d X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean On 25.05.21 19:42, Marek Behún wrote: > From: Pali Rohár > > Unfortunately the UART driver in current Linux for Armada 3700 expects > UART's parent clock to be XTAL and calculats baudrate divisor according > to XTAL clock. Therefore we must switch back to XTAL clock before > booting kernel. Do you plan to enhance the Linux driver as well to support TBG as clock in input at some time? > Implement .remove method for this driver with DM_FLAG_OS_PREPARE flag > set. > > If current baudrate is unsuitable for XTAL clock then we do not change > anything. This can only happen if the user either configured unsupported > settings or knows what they are doing and has kernel patches which allow > usage of non-XTAL parent clock. > > Signed-off-by: Pali Rohár > Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/serial/serial_mvebu_a3700.c | 67 +++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/drivers/serial/serial_mvebu_a3700.c b/drivers/serial/serial_mvebu_a3700.c > index ba2ac5917f..c7e66fef87 100644 > --- a/drivers/serial/serial_mvebu_a3700.c > +++ b/drivers/serial/serial_mvebu_a3700.c > @@ -204,6 +204,71 @@ static int mvebu_serial_probe(struct udevice *dev) > return 0; > } > > +static int mvebu_serial_remove(struct udevice *dev) > +{ > + struct mvebu_plat *plat = dev_get_plat(dev); > + void __iomem *base = plat->base; > + ulong new_parent_rate, parent_rate; > + u32 new_divider, divider; > + u32 new_oversampling; > + u32 oversampling; > + u32 d1, d2; > + > + /* > + * Switch UART base clock back to XTAL because older Linux kernel > + * expects it. Otherwise it does not calculate UART divisor correctly > + * and therefore UART does not work in kernel. > + */ > + divider = readl(base + UART_BAUD_REG); > + if (!(divider & BIT(19))) /* UART already uses XTAL */ > + return 0; > + > + /* Read current divisors settings */ > + d1 = (divider >> 15) & 7; > + d2 = (divider >> 12) & 7; > + parent_rate = plat->tbg_rate; > + divider &= 1023; > + oversampling = readl(base + UART_POSSR_REG) & 63; > + if (!oversampling) > + oversampling = 16; > + > + /* Calculate new divisor against XTAL clock without changing baudrate */ > + new_oversampling = 0; > + new_parent_rate = get_ref_clk() * 1000000; > + new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 * d2 * > + oversampling, parent_rate * 16); > + > + /* > + * UART does not work reliably when XTAL divisor is smaller than 4. > + * In this case we do not switch UART parent to XTAL. User either > + * configured unsupported settings or has newer kernel with patches > + * which allow usage of non-XTAL clock as a parent clock. > + */ > + if (new_divider < 4) > + return 0; > + > + /* > + * If new divisor is larger than maximal supported, try to switch > + * from default x16 scheme to oversampling with maximal factor 63. > + */ > + if (new_divider > 1023) { > + new_oversampling = 63; > + new_divider = DIV_ROUND_CLOSEST(new_parent_rate * divider * d1 * > + d2 * oversampling, > + parent_rate * new_oversampling); > + if (new_divider < 4 || new_divider > 1023) > + return 0; > + } > + > + while (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY)) > + ; > + > + writel(new_divider, base + UART_BAUD_REG); > + writel(new_oversampling, base + UART_POSSR_REG); > + > + return 0; > +} > + > static int mvebu_serial_of_to_plat(struct udevice *dev) > { > struct mvebu_plat *plat = dev_get_plat(dev); > @@ -232,6 +297,8 @@ U_BOOT_DRIVER(serial_mvebu) = { > .of_to_plat = mvebu_serial_of_to_plat, > .plat_auto = sizeof(struct mvebu_plat), > .probe = mvebu_serial_probe, > + .remove = mvebu_serial_remove, > + .flags = DM_FLAG_OS_PREPARE, > .ops = &mvebu_serial_ops, > }; > > Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de