Despite the title this is actually all AMD IOMMU side work; all x86
side adjustments have already been carried out.

The final few patches aren't really x2APIC related, but were found
helpful in the course of the re-work done for this version.

See individual patches for changes from v3.

01: use bit field for extended feature register
02: use bit field for control register
03: use bit field for IRTE
04: pass IOMMU to {get,free,update}_intremap_entry()
05: introduce 128-bit IRTE non-guest-APIC IRTE format
06: split amd_iommu_init_one()
07: allow enabling with IRQ not yet set up
08: adjust setup of internal interrupt for x2APIC mode
09: enable x2APIC mode when available
10: correct IRTE updating
11: don't needlessly log headers when dumping IRTs
12: miscellaneous DTE handling adjustments

Full set of patches once again attached here due to still unresolved
email issues over here.

Jan