Re: [PATCH v2 5/6] arm64: dts: qcom: Add basic devicetree support for SM8350 SoC

[Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>]

Hi Vinod,

On 2021-01-27 21:03, Vinod Koul wrote:
> Hi Sai,
> 
> On 27-01-21, 18:37, Sai Prakash Ranjan wrote:
>> Hi Vinod,
>> 
>> On 2021-01-27 18:00, Vinod Koul wrote:
> 
>> > +	timer {
>> > +		compatible = "arm,armv8-timer";
>> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
>> > IRQ_TYPE_LEVEL_LOW)>,
>> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> > +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> > +			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> 
>> The last interrupt should be hypervisor physical interrupt(10) not 
>> 12(hyp
>> virtual).
>> It works currently with android bootloaders because the host linux 
>> kernel
>> will run
>> at EL1 and will use EL1 physical timer interrupt(14), but if we ever 
>> have
>> the host
>> kernel run in EL2(for example, chrome) then we will not receive any 
>> timer
>> interrupts.
> 
> I got these values from downstream and used them as is. I will update
> and also check documentation. Thanks for pointing out

Yes looks like lot of SoC dtsi entries in downstream got it wrong.
I see upstream sm8250 also missed this. We learnt it the hard way
spending lot of time debugging why we are not able to reach the
console(because no timer interrupts) during bringup on a system
with kernel running in EL2(with VHE). I will try to reach out to
baseport guys to make sure they take care of it in future.

Thanks,
Sai

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