From: WANG Xuerui <kernel@xen0n.name>
To: Huacai Chen <chenhuacai@loongson.cn>,
Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>, Guo Ren <guoren@kernel.org>,
Xuerui Wang <kernel@xen0n.name>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Stephen Rothwell <sfr@canb.auug.org.au>
Subject: Re: [PATCH V11 06/22] LoongArch: Add CPU definition headers
Date: Wed, 18 May 2022 23:45:37 +0800 [thread overview]
Message-ID: <bfc3a1b2-af80-c619-09fc-9d0972b87bf4@xen0n.name> (raw)
In-Reply-To: <20220518092619.1269111-7-chenhuacai@loongson.cn>
On 5/18/22 17:26, Huacai Chen wrote:
> Add common headers (CPU definition and address space layout) for basic
> LoongArch support.
>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/addrspace.h | 112 ++
> arch/loongarch/include/asm/cpu-features.h | 73 +
> arch/loongarch/include/asm/cpu-info.h | 116 ++
> arch/loongarch/include/asm/cpu.h | 127 ++
> arch/loongarch/include/asm/fpregdef.h | 53 +
> arch/loongarch/include/asm/loongarch.h | 1519 +++++++++++++++++++++
> arch/loongarch/include/asm/loongson.h | 153 +++
> arch/loongarch/include/asm/regdef.h | 41 +
> 8 files changed, 2194 insertions(+)
> create mode 100644 arch/loongarch/include/asm/addrspace.h
> create mode 100644 arch/loongarch/include/asm/cpu-features.h
> create mode 100644 arch/loongarch/include/asm/cpu-info.h
> create mode 100644 arch/loongarch/include/asm/cpu.h
> create mode 100644 arch/loongarch/include/asm/fpregdef.h
> create mode 100644 arch/loongarch/include/asm/loongarch.h
> create mode 100644 arch/loongarch/include/asm/loongson.h
> create mode 100644 arch/loongarch/include/asm/regdef.h
>
> [snip]
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> new file mode 100644
> index 000000000000..2be0efe93875
> --- /dev/null
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -0,0 +1,1519 @@
>
> [snip]
>
> +
> +/* FPU register names */
> +#define LOONGARCH_FCSR0 $r0
> +#define LOONGARCH_FCSR1 $r1
> +#define LOONGARCH_FCSR2 $r2
> +#define LOONGARCH_FCSR3 $r3
Why not reuse the definitions in <asm/fpregdef.h>?
> +
> +/* FPU Status Register Values */
> +#define FPU_CSR_RSVD 0xe0e0fce0
> +
> +/*
> + * X the exception cause indicator
> + * E the exception enable
> + * S the sticky/flag bit
> + */
> +#define FPU_CSR_ALL_X 0x1f000000
> +#define FPU_CSR_INV_X 0x10000000
> +#define FPU_CSR_DIV_X 0x08000000
> +#define FPU_CSR_OVF_X 0x04000000
> +#define FPU_CSR_UDF_X 0x02000000
> +#define FPU_CSR_INE_X 0x01000000
> +
> +#define FPU_CSR_ALL_S 0x001f0000
> +#define FPU_CSR_INV_S 0x00100000
> +#define FPU_CSR_DIV_S 0x00080000
> +#define FPU_CSR_OVF_S 0x00040000
> +#define FPU_CSR_UDF_S 0x00020000
> +#define FPU_CSR_INE_S 0x00010000
> +
> +#define FPU_CSR_ALL_E 0x0000001f
> +#define FPU_CSR_INV_E 0x00000010
> +#define FPU_CSR_DIV_E 0x00000008
> +#define FPU_CSR_OVF_E 0x00000004
> +#define FPU_CSR_UDF_E 0x00000002
> +#define FPU_CSR_INE_E 0x00000001
> +
> +/* Bits 8 and 9 of FPU Status Register specify the rounding mode */
> +#define FPU_CSR_RM 0x300
> +#define FPU_CSR_RN 0x000 /* nearest */
> +#define FPU_CSR_RZ 0x100 /* towards zero */
> +#define FPU_CSR_RU 0x200 /* towards +Infinity */
> +#define FPU_CSR_RD 0x300 /* towards -Infinity */
> +
> +#define read_fcsr(source) \
> +({ \
> + unsigned int __res; \
> +\
> + __asm__ __volatile__( \
> + " movfcsr2gr %0, "__stringify(source)" \n" \
> + : "=r" (__res)); \
> + __res; \
> +})
> +
> +#define write_fcsr(dest, val) \
> +do { \
> + __asm__ __volatile__( \
> + " movgr2fcsr %0, "__stringify(dest)" \n" \
> + : : "r" (val)); \
> +} while (0)
> +
> +#endif /* _ASM_LOONGARCH_H */
> diff --git a/arch/loongarch/include/asm/loongson.h b/arch/loongarch/include/asm/loongson.h
> new file mode 100644
> index 000000000000..db4992ae6a6c
> --- /dev/null
> +++ b/arch/loongarch/include/asm/loongson.h
> @@ -0,0 +1,153 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Author: Huacai Chen <chenhuacai@loongson.cn>
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef __ASM_LOONGSON_H
> +#define __ASM_LOONGSON_H
> +
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/pci.h>
> +#include <asm/addrspace.h>
> +#include <asm/bootinfo.h>
> +
> +extern const struct plat_smp_ops loongson3_smp_ops;
> +
> +#define LOONGSON_REG(x) \
> + (*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x)))
> +
> +#define LOONGSON_LIO_BASE 0x18000000
> +#define LOONGSON_LIO_SIZE 0x00100000 /* 1M */
> +#define LOONGSON_LIO_TOP (LOONGSON_LIO_BASE+LOONGSON_LIO_SIZE-1)
> +
> +#define LOONGSON_BOOT_BASE 0x1c000000
> +#define LOONGSON_BOOT_SIZE 0x02000000 /* 32M */
> +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
> +
> +#define LOONGSON_REG_BASE 0x1fe00000
> +#define LOONGSON_REG_SIZE 0x00100000 /* 1M */
> +#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
> +
> +/* GPIO Regs - r/w */
> +
> +#define LOONGSON_GPIODATA LOONGSON_REG(0x11c)
> +#define LOONGSON_GPIOIE LOONGSON_REG(0x120)
> +#define LOONGSON_REG_GPIO_BASE (LOONGSON_REG_BASE + 0x11c)
> +
> +#define MAX_PACKAGES 16
> +
> +/* Chip Config registor of each physical cpu package */
"register" -- same below
> +extern u64 loongson_chipcfg[MAX_PACKAGES];
> +#define LOONGSON_CHIPCFG(id) (*(volatile u32 *)(loongson_chipcfg[id]))
> +
> +/* Chip Temperature registor of each physical cpu package */
> +extern u64 loongson_chiptemp[MAX_PACKAGES];
> +#define LOONGSON_CHIPTEMP(id) (*(volatile u32 *)(loongson_chiptemp[id]))
> +
> +/* Freq Control register of each physical cpu package */
> +extern u64 loongson_freqctrl[MAX_PACKAGES];
> +#define LOONGSON_FREQCTRL(id) (*(volatile u32 *)(loongson_freqctrl[id]))
> +
> +#define xconf_readl(addr) readl(addr)
> +#define xconf_readq(addr) readq(addr)
> +
> +static inline void xconf_writel(u32 val, volatile void __iomem *addr)
> +{
> + asm volatile (
> + " st.w %[v], %[hw], 0 \n"
> + " ld.b $r0, %[hw], 0 \n"
> + :
> + : [hw] "r" (addr), [v] "r" (val)
> + );
> +}
> +
> +static inline void xconf_writeq(u64 val64, volatile void __iomem *addr)
> +{
> + asm volatile (
> + " st.d %[v], %[hw], 0 \n"
> + " ld.b $r0, %[hw], 0 \n"
> + :
> + : [hw] "r" (addr), [v] "r" (val64)
> + );
> +}
> +
> +/* ============== LS7A registers =============== */
> +#define LS7A_PCH_REG_BASE 0x10000000UL
> +/* LPC regs */
> +#define LS7A_LPC_REG_BASE (LS7A_PCH_REG_BASE + 0x00002000)
> +/* CHIPCFG regs */
> +#define LS7A_CHIPCFG_REG_BASE (LS7A_PCH_REG_BASE + 0x00010000)
> +/* MISC reg base */
> +#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
> +/* ACPI regs */
> +#define LS7A_ACPI_REG_BASE (LS7A_MISC_REG_BASE + 0x00050000)
> +/* RTC regs */
> +#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
> +
> +#define LS7A_DMA_CFG (volatile void *)TO_UNCACHE(LS7A_CHIPCFG_REG_BASE + 0x041c)
> +#define LS7A_DMA_NODE_SHF 8
> +#define LS7A_DMA_NODE_MASK 0x1F00
> +
> +#define LS7A_INT_MASK_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x020)
> +#define LS7A_INT_EDGE_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x060)
> +#define LS7A_INT_CLEAR_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x080)
> +#define LS7A_INT_HTMSI_EN_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x040)
> +#define LS7A_INT_ROUTE_ENTRY_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x100)
> +#define LS7A_INT_HTMSI_VEC_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200)
> +#define LS7A_INT_STATUS_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3a0)
> +#define LS7A_INT_POL_REG (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x3e0)
> +#define LS7A_LPC_INT_CTL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2000)
> +#define LS7A_LPC_INT_ENA (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2004)
> +#define LS7A_LPC_INT_STS (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2008)
> +#define LS7A_LPC_INT_CLR (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x200c)
> +#define LS7A_LPC_INT_POL (volatile void *)TO_UNCACHE(LS7A_PCH_REG_BASE + 0x2010)
> +
> +#define LS7A_PMCON_SOC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x000)
> +#define LS7A_PMCON_RESUME_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x004)
> +#define LS7A_PMCON_RTC_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x008)
> +#define LS7A_PM1_EVT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x00c)
> +#define LS7A_PM1_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x010)
> +#define LS7A_PM1_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x014)
> +#define LS7A_PM1_TMR_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x018)
> +#define LS7A_P_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x01c)
> +#define LS7A_GPE0_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x028)
> +#define LS7A_GPE0_ENA_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x02c)
> +#define LS7A_RST_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x030)
> +#define LS7A_WD_SET_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x034)
> +#define LS7A_WD_TIMER_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x038)
> +#define LS7A_THSENS_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x04c)
> +#define LS7A_GEN_RTC_1_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x050)
> +#define LS7A_GEN_RTC_2_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x054)
> +#define LS7A_DPM_CFG_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x400)
> +#define LS7A_DPM_STS_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x404)
> +#define LS7A_DPM_CNT_REG (volatile void *)TO_UNCACHE(LS7A_ACPI_REG_BASE + 0x408)
> +
> +typedef enum {
> + ACPI_PCI_HOTPLUG_STATUS = 1 << 1,
> + ACPI_CPU_HOTPLUG_STATUS = 1 << 2,
> + ACPI_MEM_HOTPLUG_STATUS = 1 << 3,
> + ACPI_POWERBUTTON_STATUS = 1 << 8,
> + ACPI_RTC_WAKE_STATUS = 1 << 10,
> + ACPI_PCI_WAKE_STATUS = 1 << 14,
> + ACPI_ANY_WAKE_STATUS = 1 << 15,
> +} AcpiEventStatusBits;
> +
> +#define HT1LO_OFFSET 0xe0000000000UL
> +
> +/* PCI Configuration Space Base */
> +#define MCFG_EXT_PCICFG_BASE 0xefe00000000UL
> +
> +/* REG ACCESS*/
> +#define ls7a_readb(addr) (*(volatile unsigned char *)TO_UNCACHE(addr))
> +#define ls7a_readw(addr) (*(volatile unsigned short *)TO_UNCACHE(addr))
> +#define ls7a_readl(addr) (*(volatile unsigned int *)TO_UNCACHE(addr))
> +#define ls7a_readq(addr) (*(volatile unsigned long *)TO_UNCACHE(addr))
> +#define ls7a_writeb(val, addr) *(volatile unsigned char *)TO_UNCACHE(addr) = (val)
> +#define ls7a_writew(val, addr) *(volatile unsigned short *)TO_UNCACHE(addr) = (val)
> +#define ls7a_writel(val, addr) *(volatile unsigned int *)TO_UNCACHE(addr) = (val)
> +#define ls7a_writeq(val, addr) *(volatile unsigned long *)TO_UNCACHE(addr) = (val)
> +
> +#endif /* __ASM_LOONGSON_H */
> diff --git a/arch/loongarch/include/asm/regdef.h b/arch/loongarch/include/asm/regdef.h
> new file mode 100644
> index 000000000000..49a374c2612c
> --- /dev/null
> +++ b/arch/loongarch/include/asm/regdef.h
> @@ -0,0 +1,41 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
> + */
> +#ifndef _ASM_REGDEF_H
> +#define _ASM_REGDEF_H
> +
> +#define zero $r0 /* wired zero */
> +#define ra $r1 /* return address */
> +#define tp $r2
> +#define sp $r3 /* stack pointer */
> +#define a0 $r4 /* argument registers, a0/a1 reused as v0/v1 for return value */
> +#define a1 $r5
> +#define a2 $r6
> +#define a3 $r7
> +#define a4 $r8
> +#define a5 $r9
> +#define a6 $r10
> +#define a7 $r11
> +#define t0 $r12 /* caller saved */
> +#define t1 $r13
> +#define t2 $r14
> +#define t3 $r15
> +#define t4 $r16
> +#define t5 $r17
> +#define t6 $r18
> +#define t7 $r19
> +#define t8 $r20
> +#define u0 $r21
> +#define fp $r22 /* frame pointer */
> +#define s0 $r23 /* callee saved */
> +#define s1 $r24
> +#define s2 $r25
> +#define s3 $r26
> +#define s4 $r27
> +#define s5 $r28
> +#define s6 $r29
> +#define s7 $r30
> +#define s8 $r31
> +
> +#endif /* _ASM_REGDEF_H */
Apart from the minor nits:
Reviewed-by: WANG Xuerui <git@xen0n.name>
next prev parent reply other threads:[~2022-05-18 15:46 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-18 9:25 [PATCH V11 00/22] arch: Add basic LoongArch support Huacai Chen
2022-05-18 9:25 ` [PATCH V11 01/22] Documentation: LoongArch: Add basic documentations Huacai Chen
2022-05-18 15:34 ` WANG Xuerui
2022-05-18 9:25 ` [PATCH V11 02/22] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2022-05-18 15:32 ` WANG Xuerui
2022-05-20 7:37 ` Guo Ren
2022-05-20 7:43 ` WANG Xuerui
2022-05-18 9:26 ` [PATCH V11 03/22] LoongArch: Add ELF-related definitions Huacai Chen
2022-05-18 9:26 ` [PATCH V11 04/22] LoongArch: Add writecombine support for drm Huacai Chen
2022-05-18 9:26 ` Huacai Chen
2022-05-18 9:26 ` [PATCH V11 05/22] LoongArch: Add build infrastructure Huacai Chen
2022-05-18 15:22 ` WANG Xuerui
2022-05-20 7:25 ` Guo Ren
2022-05-18 9:26 ` [PATCH V11 06/22] LoongArch: Add CPU definition headers Huacai Chen
2022-05-18 15:45 ` WANG Xuerui [this message]
2022-05-18 16:12 ` Huacai Chen
2022-05-18 9:26 ` [PATCH V11 07/22] LoongArch: Add atomic/locking headers Huacai Chen
2022-05-18 15:54 ` WANG Xuerui
2022-05-20 7:54 ` Guo Ren
2022-05-20 9:50 ` Huacai Chen
2022-05-20 18:14 ` Guo Ren
2022-05-21 1:55 ` Huacai Chen
2022-05-18 9:26 ` [PATCH V11 08/22] LoongArch: Add other common headers Huacai Chen
2022-05-18 16:04 ` WANG Xuerui
2022-05-18 9:26 ` [PATCH V11 09/22] LoongArch: Add boot and setup routines Huacai Chen
2022-05-18 15:17 ` WANG Xuerui
2022-05-18 16:08 ` Huacai Chen
2022-05-20 9:17 ` Ard Biesheuvel
2022-05-20 9:41 ` Javier Martinez Canillas
2022-05-20 14:09 ` Huacai Chen
2022-05-20 14:23 ` Javier Martinez Canillas
2022-05-20 15:19 ` Huacai Chen
2022-05-20 16:32 ` Javier Martinez Canillas
2022-05-21 1:40 ` Huacai Chen
2022-05-21 7:06 ` Javier Martinez Canillas
2022-05-21 7:37 ` Huacai Chen
2022-05-21 9:06 ` Javier Martinez Canillas
2022-05-21 9:13 ` Huacai Chen
2022-05-21 9:43 ` Javier Martinez Canillas
2022-05-20 15:53 ` Huacai Chen
2022-05-24 8:27 ` Xi Ruoyao
2022-05-24 10:59 ` Huacai Chen
2022-05-24 12:48 ` 李超
2022-05-18 9:26 ` [PATCH V11 10/22] LoongArch: Add exception/interrupt handling Huacai Chen
2022-05-18 9:26 ` [PATCH V11 11/22] LoongArch: Add process management Huacai Chen
2022-05-18 9:26 ` [PATCH V11 12/22] LoongArch: Add memory management Huacai Chen
2022-05-18 9:26 ` [PATCH V11 13/22] LoongArch: Add system call support Huacai Chen
2022-05-18 9:26 ` [PATCH V11 14/22] LoongArch: Add signal handling support Huacai Chen
2022-05-18 16:13 ` WANG Xuerui
2022-05-18 16:39 ` Eric W. Biederman
2022-05-18 16:54 ` Huacai Chen
2022-05-18 17:17 ` WANG Xuerui
2022-05-18 9:26 ` [PATCH V11 15/22] LoongArch: Add ELF and module support Huacai Chen
2022-05-18 9:26 ` [PATCH V11 16/22] LoongArch: Add misc common routines Huacai Chen
2022-05-18 9:57 ` [PATCH V11 17/22] LoongArch: Add some library functions Huacai Chen
2022-05-18 9:57 ` [PATCH V11 18/22] LoongArch: Add PCI controller support Huacai Chen
2022-05-18 9:57 ` [PATCH V11 19/22] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2022-05-18 9:57 ` [PATCH V11 20/22] LoongArch: Add multi-processor (SMP) support Huacai Chen
2022-05-18 9:57 ` [PATCH V11 21/22] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2022-05-18 9:57 ` [PATCH V11 22/22] LoongArch: Add Loongson-3 default config file Huacai Chen
2022-05-18 13:42 ` [PATCH V11 00/22] arch: Add basic LoongArch support Arnd Bergmann
2022-05-18 17:18 ` Huacai Chen
2022-05-18 22:36 ` Stephen Rothwell
2022-05-22 4:18 ` WANG Xuerui
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bfc3a1b2-af80-c619-09fc-9d0972b87bf4@xen0n.name \
--to=kernel@xen0n.name \
--cc=airlied@linux.ie \
--cc=akpm@linux-foundation.org \
--cc=arnd@arndb.de \
--cc=chenhuacai@gmail.com \
--cc=chenhuacai@loongson.cn \
--cc=corbet@lwn.net \
--cc=guoren@kernel.org \
--cc=jiaxun.yang@flygoat.com \
--cc=linux-arch@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lixuefeng@loongson.cn \
--cc=luto@kernel.org \
--cc=peterz@infradead.org \
--cc=sfr@canb.auug.org.au \
--cc=siyanteng@loongson.cn \
--cc=tglx@linutronix.de \
--cc=torvalds@linux-foundation.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.