From: Jan Beulich <jbeulich@suse.com>
To: "Roger Pau Monné" <roger.pau@citrix.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
George Dunlap <george.dunlap@citrix.com>
Subject: Re: [PATCH 5/5] x86/PV32: avoid TLB flushing after mod_l3_entry()
Date: Mon, 11 Jan 2021 15:28:23 +0100 [thread overview]
Message-ID: <cf55e504-38f2-479d-524d-eb53e2f58b9b@suse.com> (raw)
In-Reply-To: <20210111142308.3fowkgtvqy4dmnli@Air-de-Roger>
On 11.01.2021 15:23, Roger Pau Monné wrote:
> On Tue, Nov 03, 2020 at 11:58:16AM +0100, Jan Beulich wrote:
>> 32-bit guests may not depend upon the side effect of using ordinary
>> 4-level paging when running on a 64-bit hypervisor. For L3 entry updates
>> to take effect, they have to use a CR3 reload. Therefore there's no need
>> to issue a paging structure invalidating TLB flush in this case.
>
> I assume it's fine for the Xen linear page tables to be lkely out of
> sync during the windows between the entry update and the CR3 reload?
Yes, because ...
> I wonder, won't something similar also apply to 64bit and L4 entries?
... unlike 64-bit paging, PAE paging special cases the treatment
of the 4 top level table entries. On bare metal they get loaded
by the CPU upon CR3 load, not when walking page tables.
Jan
next prev parent reply other threads:[~2021-01-11 14:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 10:54 [PATCH 0/5] x86/PV: memory management consistency and minor relaxations Jan Beulich
2020-11-03 10:56 ` [PATCH 1/5] x86/PV: consistently inline {,un}adjust_guest_l<N>e() Jan Beulich
2021-01-08 16:56 ` Roger Pau Monné
2020-11-03 10:56 ` [PATCH 2/5] x86/PV: fold redundant calls to adjust_guest_l<N>e() Jan Beulich
2021-01-11 10:36 ` Roger Pau Monné
2021-01-11 11:30 ` Jan Beulich
2020-11-03 10:57 ` [PATCH 3/5] x86/PV: _PAGE_RW changes may take fast path of mod_l[234]_entry() Jan Beulich
2021-01-11 11:08 ` Roger Pau Monné
2021-01-11 13:31 ` Jan Beulich
2021-01-11 14:26 ` Roger Pau Monné
2020-11-03 10:57 ` [PATCH 4/5] x86/PV: restrict TLB flushing after mod_l[234]_entry() Jan Beulich
2020-11-03 11:14 ` Andrew Cooper
2021-01-11 13:00 ` Roger Pau Monné
2021-01-11 13:22 ` Jan Beulich
2021-04-01 7:56 ` Ping: " Jan Beulich
2020-11-03 10:58 ` [PATCH 5/5] x86/PV32: avoid TLB flushing after mod_l3_entry() Jan Beulich
2021-01-11 14:23 ` Roger Pau Monné
2021-01-11 14:28 ` Jan Beulich [this message]
2021-01-11 15:57 ` Roger Pau Monné
2020-11-23 13:49 ` Ping: [PATCH 0/5] x86/PV: memory management consistency and minor relaxations Jan Beulich
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cf55e504-38f2-479d-524d-eb53e2f58b9b@suse.com \
--to=jbeulich@suse.com \
--cc=andrew.cooper3@citrix.com \
--cc=george.dunlap@citrix.com \
--cc=roger.pau@citrix.com \
--cc=wl@xen.org \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.