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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id e1sm2196056pfl.162.2020.09.10.01.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 01:12:48 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com Cc: Guo Ren Subject: [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features. Date: Thu, 10 Sep 2020 16:12:01 +0800 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f11ada3fa906..4d4f78f6a5db 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -149,4 +153,12 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.28.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E40FBC43461 for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id e1sm2196056pfl.162.2020.09.10.01.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 01:12:48 -0700 (PDT) From: Greentime Hu To: greentime.hu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, aou@eecs.berkeley.edu, palmer@dabbelt.com, paul.walmsley@sifive.com Subject: [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features. Date: Thu, 10 Sep 2020 16:12:01 +0800 Message-Id: X-Mailer: git-send-email 2.28.0 In-Reply-To: References: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200910_041251_590935_980437BC X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Guo Ren Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@linux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu Signed-off-by: Guo Ren --- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f11ada3fa906..4d4f78f6a5db 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -149,4 +153,12 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.28.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv