Re: [PATCH 5/5] drm/amdkfd: use map_queues for hiq on gfx v8 as well

[Felix Kuehling <felix.kuehling@amd.com>]

On 2020-01-10 1:37 a.m., Huang Rui wrote:
> Align with gfx v9, use map_queues packet to load hiq MQD.
>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
Please make sure you test this on a GFXv8 GPU.

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>


> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 69 ++++++++++++++++++-----
>   drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c   | 10 +++-
>   2 files changed, 63 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index bfbdded..6adac95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -207,21 +207,6 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>   
>   	acquire_queue(kgd, pipe_id, queue_id);
>   
> -	/* HIQ is set during driver init period with vmid set to 0*/
> -	if (m->cp_hqd_vmid == 0) {
> -		uint32_t value, mec, pipe;
> -
> -		mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
> -		pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
> -
> -		pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
> -			mec, pipe, queue_id);
> -		value = RREG32(mmRLC_CP_SCHEDULERS);
> -		value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1,
> -			((mec << 5) | (pipe << 3) | queue_id | 0x80));
> -		WREG32(mmRLC_CP_SCHEDULERS, value);
> -	}
> -
>   	/* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */
>   	mqd_hqd = &m->cp_mqd_base_addr_lo;
>   
> @@ -267,6 +252,59 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>   	return 0;
>   }
>   
> +static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
> +			    uint32_t pipe_id, uint32_t queue_id,
> +			    uint32_t doorbell_off)
> +{
> +	struct amdgpu_device *adev = get_amdgpu_device(kgd);
> +	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
> +	struct vi_mqd *m;
> +	uint32_t mec, pipe;
> +	int r;
> +
> +	m = get_mqd(mqd);
> +
> +	acquire_queue(kgd, pipe_id, queue_id);
> +
> +	mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1;
> +	pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec);
> +
> +	pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
> +		 mec, pipe, queue_id);
> +
> +	spin_lock(&adev->gfx.kiq.ring_lock);
> +	r = amdgpu_ring_alloc(kiq_ring, 7);
> +	if (r) {
> +		pr_err("Failed to alloc KIQ (%d).\n", r);
> +		goto out_unlock;
> +	}
> +
> +	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
> +	amdgpu_ring_write(kiq_ring,
> +			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
> +			  PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */
> +			  PACKET3_MAP_QUEUES_QUEUE(queue_id) |
> +			  PACKET3_MAP_QUEUES_PIPE(pipe) |
> +			  PACKET3_MAP_QUEUES_ME((mec - 1)) |
> +			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
> +			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
> +			  PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */
> +			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
> +	amdgpu_ring_write(kiq_ring,
> +			  PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off));
> +	amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
> +	amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
> +	amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
> +	amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
> +	amdgpu_ring_commit(kiq_ring);
> +
> +out_unlock:
> +	spin_unlock(&adev->gfx.kiq.ring_lock);
> +	release_queue(kgd);
> +
> +	return r;
> +}
> +
>   static int kgd_hqd_dump(struct kgd_dev *kgd,
>   			uint32_t pipe_id, uint32_t queue_id,
>   			uint32_t (**dump)[2], uint32_t *n_regs)
> @@ -701,6 +739,7 @@ const struct kfd2kgd_calls gfx_v8_kfd2kgd = {
>   	.set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
>   	.init_interrupts = kgd_init_interrupts,
>   	.hqd_load = kgd_hqd_load,
> +	.hiq_mqd_load = kgd_hiq_mqd_load,
>   	.hqd_sdma_load = kgd_hqd_sdma_load,
>   	.hqd_dump = kgd_hqd_dump,
>   	.hqd_sdma_dump = kgd_hqd_sdma_dump,
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> index a5e8ff1..15cbfd4 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> @@ -166,6 +166,14 @@ static int load_mqd(struct mqd_manager *mm, void *mqd,
>   					  wptr_shift, wptr_mask, mms);
>   }
>   
> +static int hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd,
> +			    uint32_t pipe_id, uint32_t queue_id,
> +			    struct queue_properties *p, struct mm_struct *mms)
> +{
> +	return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->kgd, mqd, pipe_id,
> +					      queue_id, p->doorbell_off);
> +}
> +
>   static void __update_mqd(struct mqd_manager *mm, void *mqd,
>   			struct queue_properties *q, unsigned int mtype,
>   			unsigned int atc_bit)
> @@ -438,7 +446,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type,
>   		mqd->allocate_mqd = allocate_hiq_mqd;
>   		mqd->init_mqd = init_mqd_hiq;
>   		mqd->free_mqd = free_mqd_hiq_sdma;
> -		mqd->load_mqd = load_mqd;
> +		mqd->load_mqd = hiq_load_mqd_kiq;
>   		mqd->update_mqd = update_mqd_hiq;
>   		mqd->destroy_mqd = destroy_mqd;
>   		mqd->is_occupied = is_occupied;
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