Re: [PATCH v2 1/6] cache: add sifive composable cache driver

[Sean Anderson <seanga2@gmail.com>]

On 8/3/21 12:44 AM, Zong Li wrote:
> This driver is currently responsible for enabling all ccache ways.
> Composable cache could be configure as RAM or cache, we will use it as
> RAM at the beginning to put the u-boot SPL there. In u-boot proper
> phrase, we will use the composable cache as cache, and try to enable the
> cache ways.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>   drivers/cache/Kconfig               |  7 +++
>   drivers/cache/Makefile              |  1 +
>   drivers/cache/cache-sifive-ccache.c | 75 +++++++++++++++++++++++++++++
>   3 files changed, 83 insertions(+)
>   create mode 100644 drivers/cache/cache-sifive-ccache.c
> 
> diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
> index 1e452ad6d9..40f41a817c 100644
> --- a/drivers/cache/Kconfig
> +++ b/drivers/cache/Kconfig
> @@ -39,4 +39,11 @@ config NCORE_CACHE
>   	  controller. The driver initializes cache directories and coherent
>   	  agent interfaces.
>   
> +config SIFIVE_CCACHE
> +	bool "SiFive composable cache"
> +	select CACHE
> +	help
> +	  This driver is for SiFive Composable L2/L3 cache. It enables cache
> +	  ways of composable cache.
> +
>   endmenu
> diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
> index fed50be3f9..ad765774e3 100644
> --- a/drivers/cache/Makefile
> +++ b/drivers/cache/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_SANDBOX) += sandbox_cache.o
>   obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
>   obj-$(CONFIG_NCORE_CACHE) += cache-ncore.o
>   obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
> +obj-$(CONFIG_SIFIVE_CCACHE) += cache-sifive-ccache.o
> diff --git a/drivers/cache/cache-sifive-ccache.c b/drivers/cache/cache-sifive-ccache.c
> new file mode 100644
> index 0000000000..76c0ab26ae
> --- /dev/null
> +++ b/drivers/cache/cache-sifive-ccache.c
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 SiFive
> + */
> +
> +#include <common.h>
> +#include <cache.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <dm/device.h>
> +#include <linux/bitfield.h>
> +
> +#define SIFIVE_CCACHE_CONFIG		0x000
> +#define SIFIVE_CCACHE_CONFIG_WAYS	GENMASK(15, 8)
> +
> +#define SIFIVE_CCACHE_WAY_ENABLE	0x008
> +
> +struct sifive_ccache {
> +	void __iomem *base;
> +};
> +
> +static int sifive_ccache_enable(struct udevice *dev)
> +{
> +	struct sifive_ccache *priv = dev_get_priv(dev);
> +	u32 config;
> +	u32 ways;
> +
> +	/* Enable all ways of composable cache */
> +	config = readl(priv->base + SIFIVE_CCACHE_CONFIG);
> +	ways = FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS, config);
> +
> +	writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
> +
> +	return 0;
> +}
> +
> +static int sifive_ccache_get_info(struct udevice *dev, struct cache_info *info)
> +{
> +	struct sifive_ccache *priv = dev_get_priv(dev);
> +
> +	info->base = (phys_addr_t)priv->base;
> +
> +	return 0;
> +}
> +
> +static const struct cache_ops sifive_ccache_ops = {
> +	.enable = sifive_ccache_enable,
> +	.get_info = sifive_ccache_get_info,
> +};
> +
> +static int sifive_ccache_probe(struct udevice *dev)
> +{
> +	struct sifive_ccache *priv = dev_get_priv(dev);
> +
> +	priv->base = dev_read_addr_ptr(dev);
> +	if (!priv->base)
> +		return -EINVAL;
> +
> +	return 0;
> +}
> +
> +static const struct udevice_id sifive_ccache_ids[] = {
> +	{ .compatible = "sifive,fu540-c000-ccache" },
> +	{ .compatible = "sifive,fu740-c000-ccache" },
> +	{}
> +};
> +
> +U_BOOT_DRIVER(sifive_ccache) = {
> +	.name = "sifive_ccache",
> +	.id = UCLASS_CACHE,
> +	.of_match = sifive_ccache_ids,
> +	.probe = sifive_ccache_probe,
> +	.priv_auto = sizeof(struct sifive_ccache),
> +	.ops = &sifive_ccache_ops,
> +};
> 

Reviewed-by: Sean Anderson <seanga2@gmail.com>