On Sat, 2019-02-02 at 00:08 -0800, Rodrigo Vivi wrote:
> Add more PCI Device IDs for Coffee Lake and Ice Lake.
> 
> Align with kernel commits:
> 
> 5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
> 03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice
> Lake")
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  lib/i915_pciids.h       | 8 ++++++++
>  lib/intel_device_info.c | 1 +
>  2 files changed, 9 insertions(+)
> 
> diff --git a/lib/i915_pciids.h b/lib/i915_pciids.h
> index 19266714..d2fad7b0 100644
> --- a/lib/i915_pciids.h
> +++ b/lib/i915_pciids.h
> @@ -394,6 +394,9 @@
>  	INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */
>  
>  /* CFL H */
> +#define INTEL_CFL_H_GT1_IDS(info) \
> +	INTEL_VGA_DEVICE(0x3E9C, info)
> +
>  #define INTEL_CFL_H_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
>  	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
> @@ -426,6 +429,7 @@
>  #define INTEL_CFL_IDS(info)	   \
>  	INTEL_CFL_S_GT1_IDS(info), \
>  	INTEL_CFL_S_GT2_IDS(info), \
> +	INTEL_CFL_H_GT1_IDS(info), \
>  	INTEL_CFL_H_GT2_IDS(info), \
>  	INTEL_CFL_U_GT2_IDS(info), \
>  	INTEL_CFL_U_GT3_IDS(info), \
> @@ -457,9 +461,13 @@
>  	INTEL_VGA_DEVICE(0x8A51, info), \
>  	INTEL_VGA_DEVICE(0x8A5C, info), \
>  	INTEL_VGA_DEVICE(0x8A5D, info), \
> +	INTEL_VGA_DEVICE(0x8A59, info),	\
> +	INTEL_VGA_DEVICE(0x8A58, info),	\
>  	INTEL_VGA_DEVICE(0x8A52, info), \
>  	INTEL_VGA_DEVICE(0x8A5A, info), \
>  	INTEL_VGA_DEVICE(0x8A5B, info), \
> +	INTEL_VGA_DEVICE(0x8A57, info), \
> +	INTEL_VGA_DEVICE(0x8A56, info), \
>  	INTEL_VGA_DEVICE(0x8A71, info), \
>  	INTEL_VGA_DEVICE(0x8A70, info)
>  
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 076168bf..2bca5183 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -351,6 +351,7 @@ static const struct pci_id_match
> intel_device_match[] = {
>  
>  	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
>  	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
> +	INTEL_CFL_H_GT1_IDS(&intel_coffeelake_gt1_info),
>  	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),