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Wed, 10 Mar 2021 05:53:08 -0500 (EST) Received: from localhost (disaster-area.hh.sledj.net [local]) by disaster-area.hh.sledj.net (OpenSMTPD) with ESMTPA id 80d7d3ea; Wed, 10 Mar 2021 10:53:06 +0000 (UTC) To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Subject: Re: [PATCH 3/9] hw/block/pflash_cfi02: Extract pflash_cfi02_fill_cfi_table() In-Reply-To: <20210309235028.912078-4-philmd@redhat.com> References: <20210309235028.912078-1-philmd@redhat.com> <20210309235028.912078-4-philmd@redhat.com> X-HGTTG: heart-of-gold From: David Edmondson Date: Wed, 10 Mar 2021 10:53:06 +0000 Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: softfail client-ip=64.147.123.20; envelope-from=david.edmondson@oracle.com; helo=wout4-smtp.messagingengine.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_SOFTFAIL=0.665, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Stephen Checkoway , qemu-block@nongnu.org, Max Reitz , Alistair Francis , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wednesday, 2021-03-10 at 00:50:22 +01, Philippe Mathieu-Daud=C3=A9 wrote: > Fill the CFI table in out of DeviceRealize() in a new function: > pflash_cfi02_fill_cfi_table(). > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: David Edmondson > --- > hw/block/pflash_cfi02.c | 193 +++++++++++++++++++++------------------- > 1 file changed, 99 insertions(+), 94 deletions(-) > > diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c > index fa981465e12..845f50ed99b 100644 > --- a/hw/block/pflash_cfi02.c > +++ b/hw/block/pflash_cfi02.c > @@ -724,6 +724,104 @@ static const MemoryRegionOps pflash_cfi02_ops =3D { > .endianness =3D DEVICE_NATIVE_ENDIAN, > }; >=20=20 > +static void pflash_cfi02_fill_cfi_table(PFlashCFI02 *pfl, int nb_regions) > +{ > + /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ > + const uint16_t pri_ofs =3D 0x40; > + /* Standard "QRY" string */ > + pfl->cfi_table[0x10] =3D 'Q'; > + pfl->cfi_table[0x11] =3D 'R'; > + pfl->cfi_table[0x12] =3D 'Y'; > + /* Command set (AMD/Fujitsu) */ > + pfl->cfi_table[0x13] =3D 0x02; > + pfl->cfi_table[0x14] =3D 0x00; > + /* Primary extended table address */ > + pfl->cfi_table[0x15] =3D pri_ofs; > + pfl->cfi_table[0x16] =3D pri_ofs >> 8; > + /* Alternate command set (none) */ > + pfl->cfi_table[0x17] =3D 0x00; > + pfl->cfi_table[0x18] =3D 0x00; > + /* Alternate extended table (none) */ > + pfl->cfi_table[0x19] =3D 0x00; > + pfl->cfi_table[0x1A] =3D 0x00; > + /* Vcc min */ > + pfl->cfi_table[0x1B] =3D 0x27; > + /* Vcc max */ > + pfl->cfi_table[0x1C] =3D 0x36; > + /* Vpp min (no Vpp pin) */ > + pfl->cfi_table[0x1D] =3D 0x00; > + /* Vpp max (no Vpp pin) */ > + pfl->cfi_table[0x1E] =3D 0x00; > + /* Timeout per single byte/word write (128 ms) */ > + pfl->cfi_table[0x1F] =3D 0x07; > + /* Timeout for min size buffer write (NA) */ > + pfl->cfi_table[0x20] =3D 0x00; > + /* Typical timeout for block erase (512 ms) */ > + pfl->cfi_table[0x21] =3D 0x09; > + /* Typical timeout for full chip erase (4096 ms) */ > + pfl->cfi_table[0x22] =3D 0x0C; > + /* Reserved */ > + pfl->cfi_table[0x23] =3D 0x01; > + /* Max timeout for buffer write (NA) */ > + pfl->cfi_table[0x24] =3D 0x00; > + /* Max timeout for block erase */ > + pfl->cfi_table[0x25] =3D 0x0A; > + /* Max timeout for chip erase */ > + pfl->cfi_table[0x26] =3D 0x0D; > + /* Device size */ > + pfl->cfi_table[0x27] =3D ctz32(pfl->chip_len); > + /* Flash device interface (8 & 16 bits) */ > + pfl->cfi_table[0x28] =3D 0x02; > + pfl->cfi_table[0x29] =3D 0x00; > + /* Max number of bytes in multi-bytes write */ > + /* > + * XXX: disable buffered write as it's not supported > + * pfl->cfi_table[0x2A] =3D 0x05; > + */ > + pfl->cfi_table[0x2A] =3D 0x00; > + pfl->cfi_table[0x2B] =3D 0x00; > + /* Number of erase block regions */ > + pfl->cfi_table[0x2c] =3D nb_regions; > + /* Erase block regions */ > + for (int i =3D 0; i < nb_regions; ++i) { > + uint32_t sector_len_per_device =3D pfl->sector_len[i]; > + pfl->cfi_table[0x2d + 4 * i] =3D pfl->nb_blocs[i] - 1; > + pfl->cfi_table[0x2e + 4 * i] =3D (pfl->nb_blocs[i] - 1) >> 8; > + pfl->cfi_table[0x2f + 4 * i] =3D sector_len_per_device >> 8; > + pfl->cfi_table[0x30 + 4 * i] =3D sector_len_per_device >> 16; > + } > + assert(0x2c + 4 * nb_regions < pri_ofs); > + > + /* Extended */ > + pfl->cfi_table[0x00 + pri_ofs] =3D 'P'; > + pfl->cfi_table[0x01 + pri_ofs] =3D 'R'; > + pfl->cfi_table[0x02 + pri_ofs] =3D 'I'; > + > + /* Extended version 1.0 */ > + pfl->cfi_table[0x03 + pri_ofs] =3D '1'; > + pfl->cfi_table[0x04 + pri_ofs] =3D '0'; > + > + /* Address sensitive unlock required. */ > + pfl->cfi_table[0x05 + pri_ofs] =3D 0x00; > + /* Erase suspend to read/write. */ > + pfl->cfi_table[0x06 + pri_ofs] =3D 0x02; > + /* Sector protect not supported. */ > + pfl->cfi_table[0x07 + pri_ofs] =3D 0x00; > + /* Temporary sector unprotect not supported. */ > + pfl->cfi_table[0x08 + pri_ofs] =3D 0x00; > + > + /* Sector protect/unprotect scheme. */ > + pfl->cfi_table[0x09 + pri_ofs] =3D 0x00; > + > + /* Simultaneous operation not supported. */ > + pfl->cfi_table[0x0a + pri_ofs] =3D 0x00; > + /* Burst mode not supported. */ > + pfl->cfi_table[0x0b + pri_ofs] =3D 0x00; > + /* Page mode not supported. */ > + pfl->cfi_table[0x0c + pri_ofs] =3D 0x00; > + assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); > +} > + > static void pflash_cfi02_realize(DeviceState *dev, Error **errp) > { > ERRP_GUARD(); > @@ -837,100 +935,7 @@ static void pflash_cfi02_realize(DeviceState *dev, = Error **errp) > pfl->cmd =3D 0; > pfl->status =3D 0; >=20=20 > - /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ > - const uint16_t pri_ofs =3D 0x40; > - /* Standard "QRY" string */ > - pfl->cfi_table[0x10] =3D 'Q'; > - pfl->cfi_table[0x11] =3D 'R'; > - pfl->cfi_table[0x12] =3D 'Y'; > - /* Command set (AMD/Fujitsu) */ > - pfl->cfi_table[0x13] =3D 0x02; > - pfl->cfi_table[0x14] =3D 0x00; > - /* Primary extended table address */ > - pfl->cfi_table[0x15] =3D pri_ofs; > - pfl->cfi_table[0x16] =3D pri_ofs >> 8; > - /* Alternate command set (none) */ > - pfl->cfi_table[0x17] =3D 0x00; > - pfl->cfi_table[0x18] =3D 0x00; > - /* Alternate extended table (none) */ > - pfl->cfi_table[0x19] =3D 0x00; > - pfl->cfi_table[0x1A] =3D 0x00; > - /* Vcc min */ > - pfl->cfi_table[0x1B] =3D 0x27; > - /* Vcc max */ > - pfl->cfi_table[0x1C] =3D 0x36; > - /* Vpp min (no Vpp pin) */ > - pfl->cfi_table[0x1D] =3D 0x00; > - /* Vpp max (no Vpp pin) */ > - pfl->cfi_table[0x1E] =3D 0x00; > - /* Timeout per single byte/word write (128 ms) */ > - pfl->cfi_table[0x1F] =3D 0x07; > - /* Timeout for min size buffer write (NA) */ > - pfl->cfi_table[0x20] =3D 0x00; > - /* Typical timeout for block erase (512 ms) */ > - pfl->cfi_table[0x21] =3D 0x09; > - /* Typical timeout for full chip erase (4096 ms) */ > - pfl->cfi_table[0x22] =3D 0x0C; > - /* Reserved */ > - pfl->cfi_table[0x23] =3D 0x01; > - /* Max timeout for buffer write (NA) */ > - pfl->cfi_table[0x24] =3D 0x00; > - /* Max timeout for block erase */ > - pfl->cfi_table[0x25] =3D 0x0A; > - /* Max timeout for chip erase */ > - pfl->cfi_table[0x26] =3D 0x0D; > - /* Device size */ > - pfl->cfi_table[0x27] =3D ctz32(pfl->chip_len); > - /* Flash device interface (8 & 16 bits) */ > - pfl->cfi_table[0x28] =3D 0x02; > - pfl->cfi_table[0x29] =3D 0x00; > - /* Max number of bytes in multi-bytes write */ > - /* > - * XXX: disable buffered write as it's not supported > - * pfl->cfi_table[0x2A] =3D 0x05; > - */ > - pfl->cfi_table[0x2A] =3D 0x00; > - pfl->cfi_table[0x2B] =3D 0x00; > - /* Number of erase block regions */ > - pfl->cfi_table[0x2c] =3D nb_regions; > - /* Erase block regions */ > - for (int i =3D 0; i < nb_regions; ++i) { > - uint32_t sector_len_per_device =3D pfl->sector_len[i]; > - pfl->cfi_table[0x2d + 4 * i] =3D pfl->nb_blocs[i] - 1; > - pfl->cfi_table[0x2e + 4 * i] =3D (pfl->nb_blocs[i] - 1) >> 8; > - pfl->cfi_table[0x2f + 4 * i] =3D sector_len_per_device >> 8; > - pfl->cfi_table[0x30 + 4 * i] =3D sector_len_per_device >> 16; > - } > - assert(0x2c + 4 * nb_regions < pri_ofs); > - > - /* Extended */ > - pfl->cfi_table[0x00 + pri_ofs] =3D 'P'; > - pfl->cfi_table[0x01 + pri_ofs] =3D 'R'; > - pfl->cfi_table[0x02 + pri_ofs] =3D 'I'; > - > - /* Extended version 1.0 */ > - pfl->cfi_table[0x03 + pri_ofs] =3D '1'; > - pfl->cfi_table[0x04 + pri_ofs] =3D '0'; > - > - /* Address sensitive unlock required. */ > - pfl->cfi_table[0x05 + pri_ofs] =3D 0x00; > - /* Erase suspend to read/write. */ > - pfl->cfi_table[0x06 + pri_ofs] =3D 0x02; > - /* Sector protect not supported. */ > - pfl->cfi_table[0x07 + pri_ofs] =3D 0x00; > - /* Temporary sector unprotect not supported. */ > - pfl->cfi_table[0x08 + pri_ofs] =3D 0x00; > - > - /* Sector protect/unprotect scheme. */ > - pfl->cfi_table[0x09 + pri_ofs] =3D 0x00; > - > - /* Simultaneous operation not supported. */ > - pfl->cfi_table[0x0a + pri_ofs] =3D 0x00; > - /* Burst mode not supported. */ > - pfl->cfi_table[0x0b + pri_ofs] =3D 0x00; > - /* Page mode not supported. */ > - pfl->cfi_table[0x0c + pri_ofs] =3D 0x00; > - assert(0x0c + pri_ofs < ARRAY_SIZE(pfl->cfi_table)); > + pflash_cfi02_fill_cfi_table(pfl, nb_regions); > } >=20=20 > static Property pflash_cfi02_properties[] =3D { > --=20 > 2.26.2 dme. --=20 You took the words right out of my mouth.