From: Mark Brown <broonie@kernel.org>
To: derek.fang@realtek.com
Cc: oder_chiou@realtek.com, jack.yu@realtek.com,
alsa-devel@alsa-project.org, lars@metafoo.de,
lgirdwood@gmail.com, albertchen@realtek.com,
shumingf@realtek.com, flove@realtek.com
Subject: Re: [alsa-devel] [PATCH 1/2] ASoC: rt5682: Add CCF usage for providing I2S clks
Date: Fri, 14 Feb 2020 12:38:03 +0000 [thread overview]
Message-ID: <20200214123803.GG4827@sirena.org.uk> (raw)
In-Reply-To: <1581666814-6380-1-git-send-email-derek.fang@realtek.com>
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On Fri, Feb 14, 2020 at 03:53:33PM +0800, derek.fang@realtek.com wrote:
> + parent_clk = clk_get_parent(hw->clk);
> + if (!parent_clk)
> + dev_warn(component->dev,
> + "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
> + CLK_PLL2_FIN);
> +
> + if (parent_rate != CLK_PLL2_FIN)
> + dev_warn(component->dev, "clk %s only support %d Hz input\n",
> + clk_name, CLK_PLL2_FIN);
> +
> + if (rate != CLK_48) {
> + dev_warn(component->dev, "clk %s only support %d Hz output\n",
> + clk_name, CLK_48);
> + rate = CLK_48;
> + }
Are these genuine restrictions of the hardware or is this just being
hard coded in the driver?
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next prev parent reply other threads:[~2020-02-14 12:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 7:53 [alsa-devel] [PATCH 1/2] ASoC: rt5682: Add CCF usage for providing I2S clks derek.fang
2020-02-14 7:53 ` [alsa-devel] [PATCH 2/2] ASoC: rt5682: Add DAI clock binding info for WCLK/BCLK CCF usage derek.fang
2020-02-14 12:38 ` Mark Brown [this message]
[not found] ` <b9cfe003aeb34216b59c9a22c4601bf1@realtek.com>
2020-02-17 12:36 ` [alsa-devel] [PATCH 1/2] ASoC: rt5682: Add CCF usage for providing I2S clks Mark Brown
2020-02-18 6:33 ` Derek [方德義]
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