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[156.34.48.30]) by smtp.gmail.com with ESMTPSA id l127sm620014qkc.117.2020.06.19.12.55.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jun 2020 12:55:38 -0700 (PDT) Received: from jgg by mlx with local (Exim 4.93) (envelope-from ) id 1jmN6w-00B0jt-2Q; Fri, 19 Jun 2020 16:55:38 -0300 Date: Fri, 19 Jun 2020 16:55:38 -0300 From: Jason Gunthorpe To: Felix Kuehling Subject: Re: [Linaro-mm-sig] [PATCH 04/18] dma-fence: prime lockdep annotations Message-ID: <20200619195538.GT6578@ziepe.ca> References: <20200618172338.GM6578@ziepe.ca> <20200619113934.GN6578@ziepe.ca> <20200619151551.GP6578@ziepe.ca> <20200619172308.GQ6578@ziepe.ca> <20200619180935.GA10009@redhat.com> <20200619181849.GR6578@ziepe.ca> <56008d64-772d-5757-6136-f20591ef71d2@amd.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <56008d64-772d-5757-6136-f20591ef71d2@amd.com> X-Mailman-Approved-At: Fri, 19 Jun 2020 20:02:31 +0000 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-rdma , Thomas =?utf-8?B?SGVsbHN0csO2bSAoSW50ZWwp?= , Maarten Lankhorst , LKML , DRI Development , "moderated list:DMA BUFFER SHARING FRAMEWORK" , Jerome Glisse , Thomas Hellstrom , amd-gfx list , Daniel Vetter , Daniel Vetter , "open list:DMA BUFFER SHARING FRAMEWORK" , Intel Graphics Development , Christian =?utf-8?B?S8O2bmln?= , Mika Kuoppala Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Fri, Jun 19, 2020 at 03:48:49PM -0400, Felix Kuehling wrote: > Am 2020-06-19 um 2:18 p.m. schrieb Jason Gunthorpe: > > On Fri, Jun 19, 2020 at 02:09:35PM -0400, Jerome Glisse wrote: > >> On Fri, Jun 19, 2020 at 02:23:08PM -0300, Jason Gunthorpe wrote: > >>> On Fri, Jun 19, 2020 at 06:19:41PM +0200, Daniel Vetter wrote: > >>> > >>>> The madness is only that device B's mmu notifier might need to wait > >>>> for fence_B so that the dma operation finishes. Which in turn has to > >>>> wait for device A to finish first. > >>> So, it sound, fundamentally you've got this graph of operations across > >>> an unknown set of drivers and the kernel cannot insert itself in > >>> dma_fence hand offs to re-validate any of the buffers involved? > >>> Buffers which by definition cannot be touched by the hardware yet. > >>> > >>> That really is a pretty horrible place to end up.. > >>> > >>> Pinning really is right answer for this kind of work flow. I think > >>> converting pinning to notifers should not be done unless notifier > >>> invalidation is relatively bounded. > >>> > >>> I know people like notifiers because they give a bit nicer performance > >>> in some happy cases, but this cripples all the bad cases.. > >>> > >>> If pinning doesn't work for some reason maybe we should address that? > >> Note that the dma fence is only true for user ptr buffer which predate > >> any HMM work and thus were using mmu notifier already. You need the > >> mmu notifier there because of fork and other corner cases. > > I wonder if we should try to fix the fork case more directly - RDMA > > has this same problem and added MADV_DONTFORK a long time ago as a > > hacky way to deal with it. > > > > Some crazy page pin that resolved COW in a way that always kept the > > physical memory with the mm that initiated the pin? > > > > (isn't this broken for O_DIRECT as well anyhow?) > > > > How does mmu_notifiers help the fork case anyhow? Block fork from > > progressing? > > How much the mmu_notifier blocks fork progress depends, on quickly we > can preempt GPU jobs accessing affected memory. If we don't have > fine-grained preemption capability (graphics), the best we can do is > wait for the GPU jobs to complete. We can also delay submission of new > GPU jobs to the same memory until the MMU notifier is done. Future jobs > would use the new page addresses. > > With fine-grained preemption (ROCm compute), we can preempt GPU work on > the affected adders space to minimize the delay seen by fork. > > With recoverable device page faults, we can invalidate GPU page table > entries, so device access to the affected pages stops immediately. > > In all cases, the end result is, that the device page table gets updated > with the address of the copied pages before the GPU accesses the COW > memory again.Without the MMU notifier, we'd end up with the GPU > corrupting memory of the other process. The model here in fork has been wrong for a long time, and I do wonder how O_DIRECT manages to not be broken too.. I guess the time windows there are too small to get unlucky. If you have a write pin on a page then it should not be COW'd into the fork'd process but copied with the originating page remaining with the original mm. I wonder if there is some easy way to achive that - if that is the main reason to use notifiers then it would be a better solution. Jason _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx