From: Huang Rui <ray.huang@amd.com>
To: "Du, Xiaojian" <Xiaojian.Du@amd.com>
Cc: "Wang, Kevin\(Yang\)" <Kevin1.Wang@amd.com>,
"Liang, Prike" <Prike.Liang@amd.com>,
"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
"Huang, Shimmer" <Xinmei.Huang@amd.com>,
"Zhu, Changfeng" <Changfeng.Zhu@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"Quan, Evan" <Evan.Quan@amd.com>
Subject: Re: [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
Date: Wed, 28 Oct 2020 15:21:46 +0800 [thread overview]
Message-ID: <20201028072146.GA1767271@hr-amd> (raw)
In-Reply-To: <20201027094133.21881-1-Xiaojian.Du@amd.com>
On Tue, Oct 27, 2020 at 05:41:24PM +0800, Du, Xiaojian wrote:
> This patch is to update the smu v11.5 smc header for vangogh.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++++++++++--------
> 1 file changed, 68 insertions(+), 46 deletions(-)
Series are Reviewed-by: Huang Rui <ray.huang@amd.com>
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> index 55c1b151a68d..1ada0eb64663 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> @@ -32,55 +32,77 @@
> #define PPSMC_Result_CmdRejectedBusy 0xFC
>
> // Message Definitions:
> -#define PPSMC_MSG_TestMessage 0x1
> -#define PPSMC_MSG_GetSmuVersion 0x2
> -#define PPSMC_MSG_GetDriverIfVersion 0x3
> -#define PPSMC_MSG_EnableGfxOff 0x4
> -#define PPSMC_MSG_DisableGfxOff 0x5
> -#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
> -#define PPSMC_MSG_PowerUpIspByTile 0x7
> -#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
> -#define PPSMC_MSG_PowerUpVcn 0x9
> -#define PPSMC_MSG_spare 0xA
> -#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
> -#define PPSMC_MSG_SetMinVideoGfxclkFreq 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
> -#define PPSMC_MSG_ActiveProcessNotify 0xD
> -#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
> -#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
> -#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
> -#define PPSMC_MSG_SetDriverDramAddrLow 0x11
> -#define PPSMC_MSG_TransferTableSmu2Dram 0x12
> -#define PPSMC_MSG_TransferTableDram2Smu 0x13
> -#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
> -#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
> -#define PPSMC_MSG_spare1 0x16
> -#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
> -#define PPSMC_MSG_SetMinVideoFclkFreq 0x18
> -#define PPSMC_MSG_SetSoftMinVcn 0x19
> -#define PPSMC_MSG_EnablePostCode 0x1A
> -#define PPSMC_MSG_GetGfxclkFrequency 0x1B
> -#define PPSMC_MSG_GetFclkFrequency 0x1C
> -#define PPSMC_MSG_AllowGfxOff 0x1D
> -#define PPSMC_MSG_DisallowGfxOff 0x1E
> -#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
> -#define PPSMC_MSG_SetHardMinGfxClk 0x20
> -#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
> -#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
> -#define PPSMC_MSG_SetSoftMaxVcn 0x23
> -#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM
> -#define PPSMC_MSG_SetPowerLimitPercentage 0x25
> -#define PPSMC_MSG_PowerDownJpeg 0x26
> -#define PPSMC_MSG_PowerUpJpeg 0x27
> -#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
> -#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
> -#define PPSMC_MSG_PowerUpCvip 0x2A
> -#define PPSMC_MSG_PowerDownCvip 0x2B
> -#define PPSMC_Message_Count 0x2C
> +#define PPSMC_MSG_TestMessage 0x1
> +#define PPSMC_MSG_GetSmuVersion 0x2
> +#define PPSMC_MSG_GetDriverIfVersion 0x3
> +#define PPSMC_MSG_EnableGfxOff 0x4
> +#define PPSMC_MSG_DisableGfxOff 0x5
> +#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
> +#define PPSMC_MSG_PowerUpIspByTile 0x7
> +#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
> +#define PPSMC_MSG_PowerUpVcn 0x9
> +#define PPSMC_MSG_spare 0xA
> +#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
> +#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
> +#define PPSMC_MSG_ActiveProcessNotify 0xD
> +#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
> +#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
> +#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
> +#define PPSMC_MSG_SetDriverDramAddrLow 0x11
> +#define PPSMC_MSG_TransferTableSmu2Dram 0x12
> +#define PPSMC_MSG_TransferTableDram2Smu 0x13
> +#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
> +#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
> +#define PPSMC_MSG_spare1 0x16
> +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
> +#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq
> +#define PPSMC_MSG_SetSoftMinVcn 0x19
> +#define PPSMC_MSG_EnablePostCode 0x1A
> +#define PPSMC_MSG_GetGfxclkFrequency 0x1B
> +#define PPSMC_MSG_GetFclkFrequency 0x1C
> +#define PPSMC_MSG_AllowGfxOff 0x1D
> +#define PPSMC_MSG_DisallowGfxOff 0x1E
> +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
> +#define PPSMC_MSG_SetHardMinGfxClk 0x20
> +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
> +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
> +#define PPSMC_MSG_SetSoftMaxVcn 0x23
> +#define PPSMC_MSG_spare2 0x24
> +#define PPSMC_MSG_SetPowerLimitPercentage 0x25
> +#define PPSMC_MSG_PowerDownJpeg 0x26
> +#define PPSMC_MSG_PowerUpJpeg 0x27
> +#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
> +#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
> +#define PPSMC_MSG_PowerUpCvip 0x2A
> +#define PPSMC_MSG_PowerDownCvip 0x2B
> +#define PPSMC_MSG_GetPptLimit 0x2C
> +#define PPSMC_MSG_GetThermalLimit 0x2D
> +#define PPSMC_MSG_GetCurrentTemperature 0x2E
> +#define PPSMC_MSG_GetCurrentPower 0x2F
> +#define PPSMC_MSG_GetCurrentVoltage 0x30
> +#define PPSMC_MSG_GetCurrentCurrent 0x31
> +#define PPSMC_MSG_GetAverageCpuActivity 0x32
> +#define PPSMC_MSG_GetAverageGfxActivity 0x33
> +#define PPSMC_MSG_GetAveragePower 0x34
> +#define PPSMC_MSG_GetAverageTemperature 0x35
> +#define PPSMC_MSG_SetAveragePowerTimeConstant 0x36
> +#define PPSMC_MSG_SetAverageActivityTimeConstant 0x37
> +#define PPSMC_MSG_SetAverageTemperatureTimeConstant 0x38
> +#define PPSMC_MSG_SetMitigationEndHysteresis 0x39
> +#define PPSMC_MSG_GetCurrentFreq 0x3A
> +#define PPSMC_MSG_SetReducedPptLimit 0x3B
> +#define PPSMC_MSG_SetReducedThermalLimit 0x3C
> +#define PPSMC_MSG_DramLogSetDramAddr 0x3D
> +#define PPSMC_MSG_StartDramLogging 0x3E
> +#define PPSMC_MSG_StopDramLogging 0x3F
> +#define PPSMC_MSG_SetSoftMinCclk 0x40
> +#define PPSMC_MSG_SetSoftMaxCclk 0x41
> +#define PPSMC_Message_Count 0x42
>
> //Argument for PPSMC_MSG_GpuChangeState
> enum {
> - GpuChangeState_D0Entry = 1,
> - GpuChangeState_D3Entry,
> + MODE1_RESET = 1,
> + MODE2_RESET = 2
> };
>
> #endif
> --
> 2.17.1
>
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prev parent reply other threads:[~2020-10-28 7:21 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware " Xiaojian Du
2020-10-27 9:41 ` [PATCH 03/10] drm/amd/pm: add new smc message mapping " Xiaojian Du
2020-10-27 9:41 ` [PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily Xiaojian Du
2020-10-27 9:41 ` [PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero Xiaojian Du
2020-10-27 9:41 ` [PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask " Xiaojian Du
2020-10-27 9:41 ` [PATCH 09/10] drm/amd/pm: add some swSMU functions " Xiaojian Du
2020-10-27 9:41 ` [PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU " Xiaojian Du
2020-10-28 7:21 ` Huang Rui [this message]
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