amd-gfx.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: Anson Jacob <Anson.Jacob@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
	<mikita.lipski@amd.com>,  <roman.li@amd.com>,
	<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
	<solomon.chiu@amd.com>, George Shen <george.shen@amd.com>,
	Wenjing Liu <wenjing.liu@amd.com>
Subject: [PATCH 23/24] drm/amd/display: Update VCP X.Y logging to improve usefulness
Date: Fri, 24 Sep 2021 15:09:33 -0400	[thread overview]
Message-ID: <20210924190934.1193379-24-Anson.Jacob@amd.com> (raw)
In-Reply-To: <20210924190934.1193379-1-Anson.Jacob@amd.com>

From: George Shen <george.shen@amd.com>

[Why]
Recently debugging efforts have involved setting/checking the
X.Y value used during payload allocation. Current output for
Y was calculated with incorrect bitshift. Y value is also not
human readable.

[How]
Refactor logging into separate function. Fix Y calculation error
and format output to be human readable.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 49 ++++++++++---------
 1 file changed, 25 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index f3a1219c0bb9..02c7a18c095f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3197,6 +3197,29 @@ static void update_mst_stream_alloc_table(
 				work_table[i];
 }
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+static void dc_log_vcp_x_y(const struct dc_link *link, struct fixed31_32 avg_time_slots_per_mtp)
+{
+	const uint32_t VCP_Y_PRECISION = 1000;
+	uint64_t vcp_x, vcp_y;
+
+	// Add 0.5*(1/VCP_Y_PRECISION) to round up to decimal precision
+	avg_time_slots_per_mtp = dc_fixpt_add(
+			avg_time_slots_per_mtp, dc_fixpt_from_fraction(1, 2 * VCP_Y_PRECISION));
+
+	vcp_x = dc_fixpt_floor(avg_time_slots_per_mtp);
+	vcp_y = dc_fixpt_floor(
+			dc_fixpt_mul_int(
+				dc_fixpt_sub_int(avg_time_slots_per_mtp, dc_fixpt_floor(avg_time_slots_per_mtp)),
+				VCP_Y_PRECISION));
+
+	if (link->type == dc_connection_mst_branch)
+		DC_LOG_DP2("MST Update Payload: set_throttled_vcp_size slot X.Y for MST stream "
+				"X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
+	else
+		DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream "
+				"X: %lld Y: %lld/%d", vcp_x, vcp_y, VCP_Y_PRECISION);
+}
+
 /*
  * Payload allocation/deallocation for SST introduced in DP2.0
  */
@@ -3214,18 +3237,7 @@ enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool alloca
 	if (!allocate) {
 		avg_time_slots_per_mtp = dc_fixpt_from_int(0);
 
-		DC_LOG_DP2("SST Update Payload: set_throttled_vcp_size slot X.Y for SST stream"
-				"X: %d "
-				"Y: %d",
-				dc_fixpt_floor(
-					avg_time_slots_per_mtp),
-				dc_fixpt_ceil(
-					dc_fixpt_shl(
-						dc_fixpt_sub_int(
-							avg_time_slots_per_mtp,
-							dc_fixpt_floor(
-									avg_time_slots_per_mtp)),
-						26)));
+		dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
 
 		hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
 				hpo_dp_link_encoder,
@@ -3272,18 +3284,7 @@ enum dc_status dc_link_update_sst_payload(struct pipe_ctx *pipe_ctx, bool alloca
 	if (allocate) {
 		avg_time_slots_per_mtp = calculate_sst_avg_time_slots_per_mtp(stream, link);
 
-		DC_LOG_DP2("SST Update Payload: "
-				"slot.X: %d      "
-				"slot.Y: %d",
-				dc_fixpt_floor(
-					avg_time_slots_per_mtp),
-				dc_fixpt_ceil(
-					dc_fixpt_shl(
-						dc_fixpt_sub_int(
-							avg_time_slots_per_mtp,
-							dc_fixpt_floor(
-									avg_time_slots_per_mtp)),
-						26)));
+		dc_log_vcp_x_y(link, avg_time_slots_per_mtp);
 
 		hpo_dp_link_encoder->funcs->set_throttled_vcp_size(
 				hpo_dp_link_encoder,
-- 
2.25.1


  parent reply	other threads:[~2021-09-24 19:10 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-24 19:09 [PATCH 00/24] DC Patches Sep 24, 2021 Anson Jacob
2021-09-24 19:09 ` [PATCH 01/24] drm/amd/display: use correct vpg instance for 128b/132b encoding Anson Jacob
2021-09-24 19:09 ` [PATCH 02/24] drm/amd/display: [FW Promotion] Release 0.0.85 Anson Jacob
2021-09-24 19:09 ` [PATCH 03/24] drm/amd/display: Don't enable AFMT for DP audio stream Anson Jacob
2021-09-24 19:09 ` [PATCH 04/24] drm/amd/display: add vsync notify to dmub for abm pause Anson Jacob
2021-09-24 19:09 ` [PATCH 05/24] drm/amd/display: Add debug support to override the Minimum DRAM Clock Anson Jacob
2021-09-24 19:09 ` [PATCH 06/24] drm/amd/display: update cur_lane_setting to an array one for each lane Anson Jacob
2021-09-24 19:09 ` [PATCH 07/24] drm/amd/display: add function to convert hw to dpcd lane settings Anson Jacob
2021-09-24 19:09 ` [PATCH 08/24] drm/amd/display: implement decide " Anson Jacob
2021-09-24 19:09 ` [PATCH 09/24] drm/amd/display: rename lane_settings to hw_lane_settings Anson Jacob
2021-09-24 19:09 ` [PATCH 10/24] drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings Anson Jacob
2021-09-24 19:09 ` [PATCH 11/24] drm/amd/display: add two lane settings training options Anson Jacob
2021-09-24 19:09 ` [PATCH 12/24] drm/amd/display: Fix for link encoder access for MST Anson Jacob
2021-09-24 19:09 ` [PATCH 13/24] drm/amd/display: Fix MST link encoder availability check Anson Jacob
2021-09-24 19:09 ` [PATCH 14/24] drm/amd/display: Add PPS immediate update flag for DCN2 Anson Jacob
2021-09-24 19:09 ` [PATCH 15/24] drm/amd/display: Add an extra check for dcn10 OPTC data format Anson Jacob
2021-09-24 19:09 ` [PATCH 16/24] drm/amd/display: [FW Promotion] Release 0.0.86 Anson Jacob
2021-09-24 19:09 ` [PATCH 17/24] drm/amd/display: 3.2.155 Anson Jacob
2021-09-24 19:09 ` [PATCH 18/24] drm/amd/display: Replace referral of dal with dc Anson Jacob
2021-09-24 19:09 ` [PATCH 19/24] drm/amd/display: Defer LUT memory powerdown until LUT bypass latches Anson Jacob
2021-09-24 19:09 ` [PATCH 20/24] drm/amd/display: initialize backlight_ramping_override to false Anson Jacob
2021-09-24 19:09 ` [PATCH 21/24] drm/amd/display: make verified link cap not exceeding max link cap Anson Jacob
2021-09-24 19:09 ` [PATCH 22/24] drm/amd/display: Handle Y carry-over in VCP X.Y calculation Anson Jacob
2021-09-24 19:09 ` Anson Jacob [this message]
2021-09-24 19:09 ` [PATCH 24/24] drm/amd/display: Pass PCI deviceid into DC Anson Jacob
2021-09-27 13:21 ` [PATCH 00/24] DC Patches Sep 24, 2021 Wheeler, Daniel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210924190934.1193379-24-Anson.Jacob@amd.com \
    --to=anson.jacob@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Bhawanpreet.Lakha@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=george.shen@amd.com \
    --cc=mikita.lipski@amd.com \
    --cc=qingqing.zhuo@amd.com \
    --cc=roman.li@amd.com \
    --cc=solomon.chiu@amd.com \
    --cc=stylon.wang@amd.com \
    --cc=wayne.lin@amd.com \
    --cc=wenjing.liu@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).