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charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tue, Apr 16, 2024 at 9:34=E2=80=AFAM Sunil Khatri = wrote: > > Enable redirection of irq for pagefaults for specific > clients to avoid overflow without dropping interrupts. > > So here we redirect the interrupts to another IH ring > i.e ring1 where only these interrupts are processed. > > Signed-off-by: Sunil Khatri > --- > drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/a= mdgpu/ih_v6_0.c > index 26dc99232eb6..8869aac03b82 100644 > --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c > @@ -346,6 +346,21 @@ static int ih_v6_0_irq_init(struct amdgpu_device *ad= ev) > DELAY, 3); > WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp); > > + /* Redirect the interrupts to IH RB1 fpr dGPU */ fpr -> for Alex > + if (adev->irq.ih1.ring_size) { > + tmp =3D RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_IN= DEX); > + tmp =3D REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, IND= EX, 0); > + WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp= ); > + > + tmp =3D RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DA= TA); > + tmp =3D REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIE= NT_ID, 0xa); > + tmp =3D REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOUR= CE_ID, 0x0); > + tmp =3D REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, > + SOURCE_ID_MATCH_ENABLE, 0x1); > + > + WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp)= ; > + } > + > pci_set_master(adev->pdev); > > /* enable interrupts */ > -- > 2.34.1 >