From: Viresh Kumar <viresh.kumar@linaro.org>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Viresh Kumar <vireshk@kernel.org>,
dmaengine@vger.kernel.org, Vinod Koul <vkoul@kernel.org>,
Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH v1] dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake
Date: Mon, 24 Jun 2019 09:50:21 +0530 [thread overview]
Message-ID: <20190624042021.43gbrnywzjeqnftd@vireshk-i7> (raw)
In-Reply-To: <20190621131914.38855-1-andriy.shevchenko@linux.intel.com>
On 21-06-19, 16:19, Andy Shevchenko wrote:
> Intel Elkhart Lake OSE (Offload Service Engine) provides few DMA controllers
> to the host. Enable them in the driver.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/dma/dw/pci.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c
> index c69e80d97220..7a53c6a94957 100644
> --- a/drivers/dma/dw/pci.c
> +++ b/drivers/dma/dw/pci.c
> @@ -143,6 +143,11 @@ static const struct pci_device_id dw_pci_id_table[] = {
> { PCI_VDEVICE(INTEL, 0x2286), (kernel_ulong_t)&dw_pci_data },
> { PCI_VDEVICE(INTEL, 0x22c0), (kernel_ulong_t)&dw_pci_data },
>
> + /* Elkhart Lake iDMA 32-bit (OSE DMA) */
> + { PCI_VDEVICE(INTEL, 0x4bb4), (kernel_ulong_t)&idma32_pci_data },
> + { PCI_VDEVICE(INTEL, 0x4bb5), (kernel_ulong_t)&idma32_pci_data },
> + { PCI_VDEVICE(INTEL, 0x4bb6), (kernel_ulong_t)&idma32_pci_data },
> +
> /* Haswell */
> { PCI_VDEVICE(INTEL, 0x9c60), (kernel_ulong_t)&dw_pci_data },
>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
next prev parent reply other threads:[~2019-06-24 4:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-21 13:19 [PATCH v1] dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake Andy Shevchenko
2019-06-24 4:20 ` Viresh Kumar [this message]
2019-06-25 4:33 ` Vinod Koul
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