From: Dan Carpenter <dan.carpenter@oracle.com>
To: Alexander Gordeev <a.gordeev.box@gmail.com>
Cc: devel@driverdev.osuosl.org, Michael Chen <micchen@altera.com>,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe
Date: Tue, 15 Oct 2019 16:19:55 +0300 [thread overview]
Message-ID: <20191015131955.GH4774@kadam> (raw)
In-Reply-To: <20191015112449.GA28852@AlexGordeev-DPT-VI0092>
On Tue, Oct 15, 2019 at 01:24:50PM +0200, Alexander Gordeev wrote:
> On Thu, Oct 10, 2019 at 02:30:34PM +0300, Dan Carpenter wrote:
> > On Thu, Oct 10, 2019 at 10:51:45AM +0200, Alexander Gordeev wrote:
> > > On Wed, Oct 09, 2019 at 09:53:23PM +0300, Dan Carpenter wrote:
> > > > > > > + u32 *rd_flags = hw->dma_desc_table_rd.cpu_addr->flags;
> > > > > > > + u32 *wr_flags = hw->dma_desc_table_wr.cpu_addr->flags;
> > > > > > > + struct avalon_dma_desc *desc;
> > > > > > > + struct virt_dma_desc *vdesc;
> > > > > > > + bool rd_done;
> > > > > > > + bool wr_done;
> > > > > > > +
> > > > > > > + spin_lock(lock);
>
> [*]
>
> > > > > > > +
> > > > > > > + rd_done = (hw->h2d_last_id < 0);
> > > > > > > + wr_done = (hw->d2h_last_id < 0);
> > > > > > > +
> > > > > > > + if (rd_done && wr_done) {
> > > > > > > + spin_unlock(lock);
> > > > > > > + return IRQ_NONE;
> > > > > > > + }
> > > > > > > +
> > > > > > > + do {
> > > > > > > + if (!rd_done && rd_flags[hw->h2d_last_id])
> > > > > > > + rd_done = true;
> > > > > > > +
> > > > > > > + if (!wr_done && wr_flags[hw->d2h_last_id])
> > > > > > > + wr_done = true;
> > > > > > > + } while (!rd_done || !wr_done);
Thinking about this some more, my initial instinct was still correct
actually. If we're holding the lock to prevent the CPU from writing
to it then how is hw->d2h_last_id updated in the other thread? Either
it must deadlock or it must be a race condition.
regards,
dan carpenter
next prev parent reply other threads:[~2019-10-15 13:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-09 10:12 [PATCH v2 0/2] dmaengine: avalon: Support Avalon-MM DMA Interface for PCIe Alexander Gordeev
2019-10-09 10:12 ` [PATCH v2 1/2] dmaengine: avalon: Intel " Alexander Gordeev
2019-10-09 12:14 ` Dan Carpenter
2019-10-09 14:58 ` Alexander Gordeev
2019-10-09 18:53 ` Dan Carpenter
2019-10-10 8:51 ` Alexander Gordeev
2019-10-10 11:30 ` Dan Carpenter
2019-10-15 11:24 ` Alexander Gordeev
2019-10-15 11:41 ` Dan Carpenter
2019-10-15 12:27 ` Alexander Gordeev
2019-10-15 13:19 ` Dan Carpenter [this message]
2019-10-15 14:31 ` Alexander Gordeev
2019-10-15 14:47 ` Dan Carpenter
2019-10-09 13:07 ` Greg KH
2019-10-15 10:33 ` Vinod Koul
2019-10-15 13:11 ` Alexander Gordeev
2019-10-09 10:12 ` [PATCH RFC v2 2/2] dmaengine: avalon: Intel Avalon-MM DMA Interface for PCIe test Alexander Gordeev
2019-10-09 13:08 ` Greg KH
2019-10-09 13:46 ` Dan Carpenter
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