Hi Alexander,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc5]
[cannot apply to next-20191031]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Alexander-Gordeev/dmaengine-avalon-Intel-Avalon-MM-DMA-Interface-for-PCIe/20191102-044059
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 0dbe6cb8f7e05bc9611602ef45980a6c57b245a3
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 7.4.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.4.0 make.cross ARCH=mips 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/dma/avalon/avalon-core.c: In function 'start_dma_xfer':
>> drivers/dma/avalon/avalon-core.c:115:32: warning: right shift count >= width of type [-Wshift-count-overflow]
     rc_src_hi = __table->dma_addr >> 32;
                                   ^~

vim +115 drivers/dma/avalon/avalon-core.c

    71	
    72	static int start_dma_xfer(struct avalon_dma_hw *hw,
    73				  struct avalon_dma_desc *desc)
    74	{
    75		size_t ctrl_off;
    76		struct __dma_desc_table *__table;
    77		struct dma_desc_table *table;
    78		u32 rc_src_hi, rc_src_lo;
    79		u32 ep_dst_lo, ep_dst_hi;
    80		int last_id, *__last_id;
    81		int nr_descs;
    82	
    83		if (desc->direction == DMA_TO_DEVICE) {
    84			__table = &hw->dma_desc_table_rd;
    85	
    86			ctrl_off = AVALON_DMA_RD_CTRL_OFFSET;
    87	
    88			ep_dst_hi = rd_ep_dst_hi;
    89			ep_dst_lo = rd_ep_dst_lo;
    90	
    91			__last_id = &hw->h2d_last_id;
    92		} else if (desc->direction == DMA_FROM_DEVICE) {
    93			__table = &hw->dma_desc_table_wr;
    94	
    95			ctrl_off = AVALON_DMA_WR_CTRL_OFFSET;
    96	
    97			ep_dst_hi = wr_ep_dst_hi;
    98			ep_dst_lo = wr_ep_dst_lo;
    99	
   100			__last_id = &hw->d2h_last_id;
   101		} else {
   102			return -EINVAL;
   103		}
   104	
   105		table = __table->cpu_addr;
   106		memset(&table->flags, 0, sizeof(table->flags));
   107	
   108		nr_descs = setup_dma_descs(table->descs, desc);
   109		if (nr_descs < 0)
   110			return nr_descs;
   111	
   112		last_id = nr_descs - 1;
   113		*__last_id = last_id;
   114	
 > 115		rc_src_hi = __table->dma_addr >> 32;
   116		rc_src_lo = (u32)__table->dma_addr;
   117	
   118		start_xfer(hw->regs, ctrl_off,
   119			   rc_src_hi, rc_src_lo,
   120			   ep_dst_hi, ep_dst_lo,
   121			   last_id);
   122	
   123		return 0;
   124	}
   125	

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