From: Rob Herring <robh@kernel.org>
To: Dongjiu Geng <gengdongjiu@huawei.com>
Cc: devicetree@vger.kernel.org, mturquette@baylibre.com,
dan.j.williams@intel.com, linux-clk@vger.kernel.org,
dmaengine@vger.kernel.org, vkoul@kernel.org,
p.zabel@pengutronix.de, robh+dt@kernel.org, sboyd@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller
Date: Mon, 21 Dec 2020 11:55:18 -0700 [thread overview]
Message-ID: <20201221185518.GA357293@robh.at.kernel.org> (raw)
In-Reply-To: <20201215110947.41268-4-gengdongjiu@huawei.com>
On Tue, 15 Dec 2020 11:09:46 +0000, Dongjiu Geng wrote:
> The Hiedma Controller v310 Provides eight DMA channels, each
> channel can be configured for one-way transfer. The data can
> be transferred in 8-bit, 16-bit, 32-bit, or 64-bit mode. This
> documentation describes DT bindings of this controller.
>
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> ---
> .../bindings/dma/hisilicon,hiedmacv310.yaml | 94 +++++++++++++++++++
> 1 file changed, 94 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/hisilicon,hiedmacv310.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2020-12-21 18:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 11:09 [PATCH v7 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller Dongjiu Geng
2020-12-15 11:09 ` [PATCH v7 1/4] dt-bindings: Document the hi3559a clock bindings Dongjiu Geng
2020-12-21 18:54 ` Rob Herring
2021-01-07 4:11 ` Dongjiu Geng
2020-12-15 11:09 ` [PATCH v7 2/4] clk: hisilicon: Add clock driver for hi3559A SoC Dongjiu Geng
2021-01-12 19:48 ` Stephen Boyd
2020-12-15 11:09 ` [PATCH v7 3/4] dt: bindings: dma: Add DT bindings for HiSilicon Hiedma Controller Dongjiu Geng
2020-12-21 18:55 ` Rob Herring [this message]
2020-12-15 11:09 ` [PATCH v7 4/4] dmaengine: dma: Add Hiedma Controller v310 Device Driver Dongjiu Geng
2021-01-12 12:06 ` Vinod Koul
2021-01-12 10:40 ` [PATCH v7 0/4] Enable Hi3559A SOC clock and HiSilicon Hiedma Controller Vinod Koul
2021-01-12 11:22 ` Dongjiu Geng
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