Re: [PATCH v6 4/6] dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver

From: Peter Ujfalusi <peter.ujfalusi@ti.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
	<dmaengine@vger.kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>,
	Hyun Kwon <hyun.kwon@xilinx.com>,
	Tejas Upadhyay <tejasu@xilinx.com>,
	Satish Kumar Nagireddy <SATISHNA@xilinx.com>,
	Vinod Koul <vkoul@kernel.org>
Subject: Re: [PATCH v6 4/6] dmaengine: xilinx: dpdma: Add the Xilinx DisplayPort DMA engine driver
Date: Thu, 9 Jul 2020 16:21:38 +0300	[thread overview]
Message-ID: <64817596-1ba2-97d7-1dde-600eead16b05@ti.com> (raw)
In-Reply-To: <20200708201906.4546-5-laurent.pinchart@ideasonboard.com>

Hi Laurent,

On 08/07/2020 23.19, Laurent Pinchart wrote:
> From: Hyun Kwon <hyun.kwon@xilinx.com>
> 
> The ZynqMP DisplayPort subsystem includes a DMA engine called DPDMA with
> 6 DMa channels (4 for display and 2 for audio). This driver exposes the
> DPDMA through the dmaengine API, to be used by audio (ALSA) and display
> (DRM) drivers for the DisplayPort subsystem.
> 
> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
> Signed-off-by: Tejas Upadhyay <tejasu@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

...

> +static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
> +{
> +	struct xilinx_dpdma_device *xdev = chan->xdev;
> +	struct xilinx_dpdma_sw_desc *sw_desc;
> +	struct xilinx_dpdma_tx_desc *desc;
> +	struct virt_dma_desc *vdesc;
> +	u32 reg, channels;
> +
> +	lockdep_assert_held(&chan->lock);
> +
> +	if (chan->desc.pending)
> +		return;
> +
> +	if (!chan->running) {
> +		xilinx_dpdma_chan_unpause(chan);
> +		xilinx_dpdma_chan_enable(chan);
> +		chan->first_frame = true;
> +		chan->running = true;
> +	}
> +
> +	if (chan->video_group)
> +		channels = xilinx_dpdma_chan_video_group_ready(chan);
> +	else
> +		channels = BIT(chan->id);
> +
> +	if (!channels)
> +		return;
> +
> +	vdesc = vchan_next_desc(&chan->vchan);
> +	if (!vdesc)
> +		return;
> +
> +	if (!chan->first_frame && !(vdesc->tx.flags & DMA_PREP_LOAD_EOT)) {
> +		/*
> +		 * The client forgot to set the DMA_PREP_LOAD_EOT flag. The DMA
> +		 * engine API requires the channel to silently ignore the
> +		 * descriptor, leaving the client waiting forever for the new
> +		 * descriptor to be processed.
> +		 */

This hardly going to happen. But if it does, a gentle dev_dbg() might
save some time for the user on debugging?

> +		return;
> +	}
> +
> +	desc = to_dpdma_tx_desc(vdesc);
> +	chan->desc.pending = desc;
> +	list_del(&desc->vdesc.node);
> +
> +	/*
> +	 * Assign the cookie to descriptors in this transaction. Only 16 bit
> +	 * will be used, but it should be enough.
> +	 */
> +	list_for_each_entry(sw_desc, &desc->descriptors, node)
> +		sw_desc->hw.desc_id = desc->vdesc.tx.cookie;
> +
> +	sw_desc = list_first_entry(&desc->descriptors,
> +				   struct xilinx_dpdma_sw_desc, node);
> +	dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR,
> +		    lower_32_bits(sw_desc->dma_addr));
> +	if (xdev->ext_addr)
> +		dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE,
> +			    FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK,
> +				       upper_32_bits(sw_desc->dma_addr)));
> +
> +	if (chan->first_frame)
> +		reg = XILINX_DPDMA_GBL_TRIG_MASK(channels);
> +	else
> +		reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels);
> +
> +	chan->first_frame = false;
> +
> +	dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg);
> +}

- Péter

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