Re: [PATCH v7 0/5] Add shared workqueue support for idxd driver

[Dave Jiang <dave.jiang@intel.com>]

On 10/7/2020 12:01 AM, Vinod Koul wrote:
> On 05-10-20, 08:11, Dave Jiang wrote:
> 
>> == Background ==
>> A typical DMA device requires the driver to translate application buffers to hardware addresses,
>> and a kernel-user transition to notify the hardware of new work. Shared Virtual Addressing (SVA)
>> allows the processor and device to use the same virtual addresses without requiring software to
>> translate between the address spaces. ENQCMD is a new instruction on Intel Platforms that allows
>> user applications to directly notify hardware of new work, much like how doorbells are used in
>> some hardware, but it carries a payload along with it. ENQCMDS is the supervisor version (ring0)
>> of ENQCMD.
>>
>> == ENQCMDS ==
>> Introduce enqcmds(), a helper funciton that copies an input payload to a 64B aligned
>> destination and confirms whether the payload was accepted by the device or not.
>> enqcmds() wraps the new ENQCMDS CPU instruction. The ENQCMDS is a ring 0 CPU instruction that
>> performs similar to the ENQCMD instruction. Descriptor submission must use ENQCMD(S) for shared
>> workqueues (swq) on an Intel DSA device.
>>
>> == Shared WQ support ==
>> Introduce shared workqueue (swq) support for the idxd driver. The current idxd driver contains
>> dedicated workqueue (dwq) support only. A dwq accepts descriptors from a MOVDIR64B instruction.
>> MOVDIR64B is a posted instruction on the PCIe bus, it does not wait for any response from the
>> device. If the wq is full, submitted descriptors are dropped. A swq utilizes the ENQCMDS in
>> ring 0, which is a non-posted instruction. The zero flag would be set to 1 if the device rejects
>> the descriptor or if the wq is full. A swq can be shared between multiple users
>> (kernel or userspace) due to not having to keep track of the wq full condition for submission.
>> A swq requires PASID and can only run with SVA support.
>>
>> == IDXD SVA support ==
>> Add utilization of PASID to support Shared Virtual Addressing (SVA). With PASID support,
>> the descriptors can be programmed with host virtual address (HVA) rather than IOVA.
>> The hardware will work with the IOMMU in fulfilling page requests. With SVA support,
>> a user app using the char device interface can now submit descriptors without having to pin the
>> virtual memory range it wants to DMA in its own address space.
>>
>> The series does not add SVA support for the dmaengine subsystem. That support is coming at a
>> later time.
> 
> Applied, thanks
> 

Thanks Vinod!