From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.7 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC67DC76186 for ; Wed, 17 Jul 2019 14:16:51 +0000 (UTC) Received: from dpdk.org (dpdk.org [92.243.14.124]) by mail.kernel.org (Postfix) with ESMTP id 23F9A20818 for ; Wed, 17 Jul 2019 14:16:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 23F9A20818 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0B0251B9DF; Wed, 17 Jul 2019 16:16:50 +0200 (CEST) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id E45541B9D9 for ; Wed, 17 Jul 2019 16:16:47 +0200 (CEST) Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 441BC3082145; Wed, 17 Jul 2019 14:16:47 +0000 (UTC) Received: from dhcp-25.97.bos.redhat.com (unknown [10.18.25.22]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 93E591001B02; Wed, 17 Jul 2019 14:16:46 +0000 (UTC) From: Aaron Conole To: Nagadheeraj Rottela Cc: "dev\@dpdk.org" , Srikanth Jampala References: <20190717052837.647-1-rnagadheeraj@marvell.com> <20190717052837.647-9-rnagadheeraj@marvell.com> Date: Wed, 17 Jul 2019 10:16:45 -0400 In-Reply-To: <20190717052837.647-9-rnagadheeraj@marvell.com> (Nagadheeraj Rottela's message of "Wed, 17 Jul 2019 05:29:12 +0000") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.42]); Wed, 17 Jul 2019 14:16:47 +0000 (UTC) Subject: Re: [dpdk-dev] [PATCH 08/10] crypto/nitrox: add burst enqueue and dequeue operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Nagadheeraj Rottela writes: > Add burst enqueue and dequeue operations along with interface for > symmetric request manager. > > Signed-off-by: Nagadheeraj Rottela > --- Hi Nagadheeraj, > drivers/crypto/nitrox/nitrox_qp.h | 55 ++++++++++ > drivers/crypto/nitrox/nitrox_sym.c | 123 ++++++++++++++++++++- > drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 173 ++++++++++++++++++++++++= ++++++ > drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 10 ++ > 4 files changed, 359 insertions(+), 2 deletions(-) > > diff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/ni= trox_qp.h > index 0244c4dbf..645fa8925 100644 > --- a/drivers/crypto/nitrox/nitrox_qp.h > +++ b/drivers/crypto/nitrox/nitrox_qp.h > @@ -34,12 +34,67 @@ struct nitrox_qp { > rte_atomic16_t pending_count; > }; >=20=20 > +static inline uint16_t > +nitrox_qp_free_count(struct nitrox_qp *qp) > +{ > + uint16_t pending_count =3D rte_atomic16_read(&qp->pending_count); > + > + RTE_ASSERT(qp->count >=3D pending_count); > + return (qp->count - pending_count); > +} > + > static inline bool > nitrox_qp_is_empty(struct nitrox_qp *qp) > { > return (rte_atomic16_read(&qp->pending_count) =3D=3D 0); > } >=20=20 > +static inline uint16_t > +nitrox_qp_used_count(struct nitrox_qp *qp) > +{ > + return rte_atomic16_read(&qp->pending_count); > +} > + > +static inline struct nitrox_softreq * > +nitrox_qp_get_softreq(struct nitrox_qp *qp) > +{ > + uint32_t tail =3D qp->tail % qp->count; > + > + return qp->ridq[tail].sr; > +} > + > +static inline void > +nitrox_ring_dbell(struct nitrox_qp *qp, uint16_t cnt) > +{ > + struct command_queue *cmdq =3D &qp->cmdq; > + > + if (!cnt) > + return; > + > + rte_write64(cnt, cmdq->dbell_csr_addr); > +} > + > +static inline void > +nitrox_qp_enqueue(struct nitrox_qp *qp, void *instr, struct nitrox_softr= eq *sr) > +{ > + uint32_t head =3D qp->head % qp->count; > + > + memcpy(&qp->cmdq.ring[head * qp->cmdq.instr_size], > + instr, qp->cmdq.instr_size); > + qp->ridq[head].sr =3D sr; > + qp->head++; > + rte_atomic16_inc(&qp->pending_count); > + rte_wmb(); > +} > + > +static inline void > +nitrox_qp_dequeue(struct nitrox_qp *qp) > +{ > + qp->tail++; > + rte_atomic16_dec(&qp->pending_count); > + rte_smp_mb(); > +} > + > int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, > const char *dev_name, uint32_t nb_descriptors, > uint8_t inst_size, int socket_id); > diff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/n= itrox_sym.c > index 34c62b02e..9ccc28755 100644 > --- a/drivers/crypto/nitrox/nitrox_sym.c > +++ b/drivers/crypto/nitrox/nitrox_sym.c > @@ -521,6 +521,125 @@ nitrox_sym_dev_sess_clear(struct rte_cryptodev *cde= v, > rte_mempool_put(sess_mp, ctx); > } >=20=20 > +static struct nitrox_crypto_ctx * > +get_crypto_ctx(struct rte_crypto_op *op) > +{ > + if (op->sess_type =3D=3D RTE_CRYPTO_OP_WITH_SESSION) { > + if (likely(op->sym->session)) > + return get_sym_session_private_data(op->sym->session, > + nitrox_sym_drv_id); > + > + } > + > + return NULL; > +} > + > +static int > +nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_crypto_op *op) > +{ > + struct nitrox_crypto_ctx *ctx; > + struct nitrox_softreq *sr; > + int err; > + > + op->status =3D RTE_CRYPTO_OP_STATUS_NOT_PROCESSED; > + > + ctx =3D get_crypto_ctx(op); > + if (unlikely(!ctx)) { > + op->status =3D RTE_CRYPTO_OP_STATUS_INVALID_SESSION; > + return -EINVAL; > + } > + > + if (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr))) > + return -ENOMEM; > + > + err =3D nitrox_process_se_req(qp->qno, op, ctx, sr); > + if (unlikely(err)) { > + rte_mempool_put(qp->sr_mp, sr); > + op->status =3D RTE_CRYPTO_OP_STATUS_ERROR; > + return err; > + } > + > + nitrox_qp_enqueue(qp, nitrox_sym_instr_addr(sr), sr); > + return 0; > +} > + > +static uint16_t > +nitrox_sym_dev_enq_burst(void *queue_pair, struct rte_crypto_op **ops, > + uint16_t nb_ops) > +{ > + struct nitrox_qp *qp =3D queue_pair; > + uint16_t free_slots =3D 0; > + uint16_t cnt =3D 0; > + bool err =3D false; > + > + free_slots =3D nitrox_qp_free_count(qp); > + if (nb_ops > free_slots) > + nb_ops =3D free_slots; > + > + for (cnt =3D 0; cnt < nb_ops; cnt++) { > + if (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) { > + err =3D true; > + break; > + } > + } > + > + nitrox_ring_dbell(qp, cnt); > + qp->stats.enqueued_count +=3D cnt; > + if (unlikely(err)) > + qp->stats.enqueue_err_count++; > + > + return cnt; > +} > + > +static int > +nitrox_deq_single_op(struct nitrox_qp *qp, struct rte_crypto_op **op_ptr) > +{ > + struct nitrox_softreq *sr; > + int ret; > + struct rte_crypto_op *op; > + > + sr =3D nitrox_qp_get_softreq(qp); > + ret =3D nitrox_check_se_req(sr, op_ptr); > + if (ret < 0) > + return -EAGAIN; > + > + op =3D *op_ptr; > + nitrox_qp_dequeue(qp); > + rte_mempool_put(qp->sr_mp, sr); > + if (!ret) { > + op->status =3D RTE_CRYPTO_OP_STATUS_SUCCESS; > + qp->stats.dequeued_count++; > + > + return 0; > + } > + > + if (ret =3D=3D MC_MAC_MISMATCH_ERR_CODE) > + op->status =3D RTE_CRYPTO_OP_STATUS_AUTH_FAILED; > + else > + op->status =3D RTE_CRYPTO_OP_STATUS_ERROR; > + qp->stats.dequeue_err_count++; > + > + return 0; > +} > + > +static uint16_t > +nitrox_sym_dev_deq_burst(void *queue_pair, struct rte_crypto_op **ops, > + uint16_t nb_ops) > +{ > + struct nitrox_qp *qp =3D queue_pair; > + uint16_t filled_slots =3D nitrox_qp_used_count(qp); > + int cnt =3D 0; > + > + if (nb_ops > filled_slots) > + nb_ops =3D filled_slots; > + > + for (cnt =3D 0; cnt < nb_ops; cnt++) > + if (nitrox_deq_single_op(qp, &ops[cnt])) > + break; > + > + return cnt; > +} > + > static struct rte_cryptodev_ops nitrox_cryptodev_ops =3D { > .dev_configure =3D nitrox_sym_dev_config, > .dev_start =3D nitrox_sym_dev_start, > @@ -565,8 +684,8 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev) > ndev->rte_sym_dev.name =3D cdev->data->name; > cdev->driver_id =3D nitrox_sym_drv_id; > cdev->dev_ops =3D &nitrox_cryptodev_ops; > - cdev->enqueue_burst =3D NULL; > - cdev->dequeue_burst =3D NULL; > + cdev->enqueue_burst =3D nitrox_sym_dev_enq_burst; > + cdev->dequeue_burst =3D nitrox_sym_dev_deq_burst; > cdev->feature_flags =3D RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | > RTE_CRYPTODEV_FF_HW_ACCELERATED | > RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | > diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/n= itrox/nitrox_sym_reqmgr.c > index 42d67317c..87d08a0c1 100644 > --- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c > +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c > @@ -9,7 +9,107 @@ > #include "nitrox_sym_reqmgr.h" > #include "nitrox_logs.h" >=20=20 > +#define PENDING_SIG 0xFFFFFFFFFFFFFFFFUL > +#define CMD_TIMEOUT 2 > + > +union pkt_instr_hdr { > + uint64_t value; > + struct { > +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN > + uint64_t raz_48_63 : 16; > + uint64_t g : 1; > + uint64_t gsz : 7; > + uint64_t ihi : 1; > + uint64_t ssz : 7; > + uint64_t raz_30_31 : 2; > + uint64_t fsz : 6; > + uint64_t raz_16_23 : 8; > + uint64_t tlen : 16; > +#else > + uint64_t tlen : 16; > + uint64_t raz_16_23 : 8; > + uint64_t fsz : 6; > + uint64_t raz_30_31 : 2; > + uint64_t ssz : 7; > + uint64_t ihi : 1; > + uint64_t gsz : 7; > + uint64_t g : 1; > + uint64_t raz_48_63 : 16; > +#endif > + } s; > +}; > + > +union pkt_hdr { > + uint64_t value[2]; > + struct { > +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN > + uint64_t opcode : 8; > + uint64_t arg : 8; > + uint64_t ctxc : 2; > + uint64_t unca : 1; > + uint64_t raz_44 : 1; > + uint64_t info : 3; > + uint64_t destport : 9; > + uint64_t unc : 8; > + uint64_t raz_19_23 : 5; > + uint64_t grp : 3; > + uint64_t raz_15 : 1; > + uint64_t ctxl : 7; > + uint64_t uddl : 8; > +#else > + uint64_t uddl : 8; > + uint64_t ctxl : 7; > + uint64_t raz_15 : 1; > + uint64_t grp : 3; > + uint64_t raz_19_23 : 5; > + uint64_t unc : 8; > + uint64_t destport : 9; > + uint64_t info : 3; > + uint64_t raz_44 : 1; > + uint64_t unca : 1; > + uint64_t ctxc : 2; > + uint64_t arg : 8; > + uint64_t opcode : 8; > +#endif > + uint64_t ctxp; > + } s; > +}; > + > +union slc_store_info { > + uint64_t value[2]; > + struct { > +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN > + uint64_t raz_39_63 : 25; > + uint64_t ssz : 7; > + uint64_t raz_0_31 : 32; > +#else > + uint64_t raz_0_31 : 32; > + uint64_t ssz : 7; > + uint64_t raz_39_63 : 25; > +#endif > + uint64_t rptr; > + } s; > +}; > + > +struct nps_pkt_instr { > + uint64_t dptr0; > + union pkt_instr_hdr ih; > + union pkt_hdr irh; > + union slc_store_info slc; > + uint64_t fdata[2]; > +}; > + > +struct resp_hdr { > + uint64_t orh; > + uint64_t completion; > +}; > + > struct nitrox_softreq { > + struct nitrox_crypto_ctx *ctx; > + struct rte_crypto_op *op; > + struct nps_pkt_instr instr; > + struct resp_hdr resp; > + uint64_t timeout; > rte_iova_t iova; > }; >=20=20 > @@ -20,6 +120,79 @@ softreq_init(struct nitrox_softreq *sr, rte_iova_t io= va) > sr->iova =3D iova; > } >=20=20 > +static int > +process_cipher_auth_data(struct nitrox_softreq *sr) > +{ > + RTE_SET_USED(sr); > + return 0; > +} > + > +static int > +process_softreq(struct nitrox_softreq *sr) > +{ > + struct nitrox_crypto_ctx *ctx =3D sr->ctx; > + int err =3D 0; > + > + switch (ctx->nitrox_chain) { > + case NITROX_CHAIN_CIPHER_AUTH: > + case NITROX_CHAIN_AUTH_CIPHER: > + err =3D process_cipher_auth_data(sr); > + break; > + default: > + err =3D -EINVAL; > + break; > + } > + > + return err; > +} > + > +int > +nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op, > + struct nitrox_crypto_ctx *ctx, > + struct nitrox_softreq *sr) > +{ > + RTE_SET_USED(qno); > + softreq_init(sr, sr->iova); > + sr->ctx =3D ctx; > + sr->op =3D op; > + process_softreq(sr); > + sr->timeout =3D rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz= (); > + return 0; > +} On AARCH64 builds, I see the following error: ../drivers/crypto/nitrox/nitrox_sym_reqmgr.c: In function =E2=80=98nitrox_p= rocess_se_req=E2=80=99: ../drivers/crypto/nitrox/nitrox_sym_reqmgr.c:582:16: error: implicit declar= ation of function =E2=80=98rte_get_timer_cycles=E2=80=99 [-Werror=3Dimplici= t-function-declaration] sr->timeout =3D rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz(); ^ ../drivers/crypto/nitrox/nitrox_sym_reqmgr.c:582:55: error: implicit declar= ation of function =E2=80=98rte_get_timer_hz=E2=80=99 [-Werror=3Dimplicit-fu= nction-declaration] sr->timeout =3D rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz(); ^ ../drivers/crypto/nitrox/nitrox_sym_reqmgr.c: In function =E2=80=98nitrox_c= heck_se_req=E2=80=99: ../drivers/crypto/nitrox/nitrox_sym_reqmgr.c:600:34: error: comparison betw= een signed and unsigned integer expressions [-Werror=3Dsign-compare] else if (rte_get_timer_cycles() < sr->timeout) Is it possible that there is a missing include? > +int > +nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op **op) > +{ > + uint64_t cc; > + uint64_t orh; > + int err; > + > + rte_rmb(); > + cc =3D *(volatile uint64_t *)(&sr->resp.completion); > + orh =3D *(volatile uint64_t *)(&sr->resp.orh); > + if (cc !=3D PENDING_SIG) > + err =3D 0; > + else if ((orh !=3D PENDING_SIG) && (orh & 0xff)) > + err =3D orh & 0xff; > + else if (rte_get_timer_cycles() < sr->timeout) > + return -EAGAIN; > + else > + err =3D 0xff; > + > + if (unlikely(err)) > + NITROX_LOG(ERR, "Request err 0x%x, orh 0x%"PRIx64"\n", err, > + sr->resp.orh); > + > + *op =3D sr->op; > + return err; > +} > + > +void * > +nitrox_sym_instr_addr(struct nitrox_softreq *sr) > +{ > + return &sr->instr; > +} > + > static void > req_pool_obj_init(__rte_unused struct rte_mempool *mp, > __rte_unused void *opaque, void *obj, > diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/n= itrox/nitrox_sym_reqmgr.h > index 5953c958c..fa2637bdb 100644 > --- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h > +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h > @@ -5,6 +5,16 @@ > #ifndef _NITROX_SYM_REQMGR_H_ > #define _NITROX_SYM_REQMGR_H_ >=20=20 > +#include "nitrox_sym_ctx.h" > + > +struct nitrox_qp; > +struct nitrox_softreq; > + > +int nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op, > + struct nitrox_crypto_ctx *ctx, > + struct nitrox_softreq *sr); > +int nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op = **op); > +void *nitrox_sym_instr_addr(struct nitrox_softreq *sr); > struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cde= v, > uint32_t nobjs, uint16_t qp_id, > int socket_id);