From mboxrd@z Thu Jan 1 00:00:00 1970 From: CK Hu Subject: Re: [PATCH V6 0/8] make mt7623 clock of hdmi stable Date: Wed, 6 Mar 2019 09:52:21 +0800 Message-ID: <1551837141.23995.13.camel@mtksdaap41> References: <20190225020912.29120-1-wangyan.wang@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190225020912.29120-1-wangyan.wang@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: wangyan wang Cc: Michael Turquette , Stephen Boyd , Matthias Brugger , Philipp Zabel , David Airlie , Daniel Vetter , chunhui dai , Colin Ian King , Sean Wang , Ryder Lee , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, dri-devel@lists.freedesktop.org, srv_heupstream@mediatek.com List-Id: dri-devel@lists.freedesktop.org On Mon, 2019-02-25 at 10:09 +0800, wangyan wang wrote: > From: Wangyan Wang > > V6 adopt maintainer's suggestion. > Here is the change list between V5 & V6 > 1. change "unsigned char mux_flags;" to "u8 mux_flags;" to > match with the struct in " clk: mediatek: add MUX_GATE_FLAGS_2". > Hi, Wangyan: I'm not familiar with this clock system, so I still have some question about it, if you could describe more clear, it would help us to speed up this review process. In [1], I find the clock that dpi and hdmi_phy controls, dpi0: dpi@14014000 { clocks = <&mmsys CLK_MM_DPI1_DIGL>, <&mmsys CLK_MM_DPI1_ENGINE>, <&topckgen CLK_TOP_TVDPLL>; clock-names = "pixel", "engine", "pll"; }; hdmi_phy: phy@10209100 { clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; clock-names = "pll_ref"; }; In [2], You say that to prevent changing tvdpll would let hdmi stable, and this clock is controlled by dpi, why do you modify the control flow in hdmi_phy? If these two have relationship, please describe more clear because I'm not familiar with this clock system. And I think that patch 'drm/mediatek: using new factor for tvdpll in MT2701' is the major patch to prevent modifying tvdpll because it reduce the factor case. Does MT8173 has the same problem? Just ask, I does not require you to modify MT8173 part. [1] https://github.com/frank-w/BPI-R2-4.14/blob/663f7def421952eb49b2d698eadaff12d02622d2/arch/arm/boot/dts/mt7623.dtsi [2] http://lists.infradead.org/pipermail/linux-mediatek/2019-February/017693.html Regards, CK > > chunhui dai (8): > drm/mediatek: recalculate hdmi phy clock of MT2701 by querying > hardware > drm/mediatek: move the setting of fixed divider > drm/mediatek: using different flags of clk for HDMI phy > drm/mediatek: fix the rate and divder of hdmi phy for MT2701 > clk: mediatek: add MUX_GATE_FLAGS_2 > clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel > drm/mediatek: using new factor for tvdpll in MT2701 > drm/mediatek: fix the rate of parent for hdmi phy in MT2701 > > drivers/clk/mediatek/clk-mt2701.c | 4 +- > drivers/clk/mediatek/clk-mtk.c | 2 +- > drivers/clk/mediatek/clk-mtk.h | 20 ++++++--- > drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++-- > drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------ > drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +--- > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++--- > drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++ > 8 files changed, 102 insertions(+), 52 deletions(-) >